CODEWITHSUNDEEP
verilogfpgasystem-verilog
user4611785
user4611785

Reputation: 31

Inbuilt Adders used in FPGA

When we write code for adder C=A+B then which adders are used by IST for implementation in FPGA . Can we build adders faster than that so that our delay gets reduced by compromising the Area.

Upvotes: 0

Views: 161

Answers (1)

Kevin Thibedeau
Kevin Thibedeau

Reputation: 3411

For most cases you can't beat the dedicated adder resources found in FPGAs. They have enhanced carry logic that is significantly faster than what you can create in the configurable fabric. In certain cases you may be able to do better than the hardware adder support if you switch to an architecture that is less sensitive to carry delays such as using the signed digit number system to add multiple values together. The overhead of doing that with only two terms will still be slower though.

Upvotes: 3

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