CODEWITHSUNDEEP
vhdl
jimparsons
jimparsons

Reputation: 49

Tips and tricks for vhdl design debugging

I have been using VHDL for a while, and i found that , its more difficult to debug a VHDL design than to design it. Since processes are concurrent , its very difficult to know which part of the design has bugs.

Like C , where we can use some easy degugging rules like putting a printf statement to see the bug location, is there any simple tips and tricks to find such errors in VHDL.

Please also suggest me any website or do document , which can be used for the same.

Upvotes: 1

Views: 1051

Answers (2)

Ran Levi
Ran Levi

Reputation: 71

Relative to other programming languages (such as C, Python, etc.), I actually find VHDL easier to debug. the language itself is rather simple, in the sense that it doesn't lend itself to creating complicated algorithms very easily. The secret to easy debugging, in my experience, is to keep modules as simple as possible, and combine them together to create complicated structures. this way, finding bugs gets easier.

Upvotes: 2

scary_jeff
scary_jeff

Reputation: 4374

This question is perhaps a bit vague, but here's a few things that I try to do to make designs easier to work on. It's opinion based, but does come from personal experience.

  • Write test benches for your modules. Testing is a very big subject that I won't try to cover in depth, but you should have some sort of testing in place, so that you can evaluate your design in a simulator. For anything but a trivial design, finding problems in your code is far easier and faster in a simulator than on your target PCB.
  • Keep the design modular. As with any programming really, you shouldn't normally have huge 3000 line files, as it becomes difficult to hold the functionality in your head in one go. An exception to this might be a lookup table; even then, I would tend to put the table in its own file with nothing else, to keep the 'real', functional code more readable.

  • You can use simple assertions to catch some types of problem during simulation. Example:

    if (rising_edge(clk)) then
    assert (a /= b)
        report "a and b should never be equal!"
        severity error;
end if;

  • Similarly, you can use the report statement on its own, to print out signal values. Example:

    if (rising_edge(clk)) then
    report "count is now " & integer'image(count);
end if;

    Report doesn't do anything in your compiled FPGA, it's only for simulation.

  • If you already have test benches for your design, and it's still proving hard to debug, try writing simple test benches for individual modules within the design. With programming in C or another language, you wouldn't wait until your program was finished before doing any testing; you would keep testing new functionality as you write it. The equivalent in VHDL would be to test individual modules as you write them, before assembling them to form more complex functionality.
  • Try some more advanced verification techniques. Your simulator can probably generate code coverage metrics for a start. Beyond that, there are several methodologies for improving your tests, such as constrained random testing, self checking tests, assertion based verification, and many more. This is a whole topic in itself.

Upvotes: 7

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