CODEWITHSUNDEEP
verilogfpgahdl
Tusher
Tusher

Reputation: 41

How to store input into reg from wire in verilog?

I' trying to store value from wire named 'in' into reg 'a'. But, the problem is value of reg 'a' is showing 'xxxx' in simulator. However, value of wire 'in' is showing correctly. My target is just to read value from input wire and store it into a register. 

module test(
input [3:0] in,
output [3:0] out
);
reg [3:0] a;

initial
begin
a = in;
end
endmodule

Upvotes: 2

Views: 26075

Answers (1)

mkrieger1
mkrieger1

Reputation: 23264

The reason why the value of a is 'xxxx' in the simulation is probably that a is set to the value of in only a single time initially, and a may not yet have been set to any specific value at this time in the simulation.

Declaring a reg in Verilog does not necessarily mean that a hardware register is described by the code. That usually involves the use of a clock signal:

module test(
  input clk,
  input [3:0] in,
  output [3:0] out
);

// this describes a register with input "in" and output "a"
reg [3:0] a;
always @(posedge clk) begin
  a <= in;
end

// I assume you want "a" to be the output of the module
assign out = a;

endmodule

Here is a counter example where a reg is used to describe something which is not a register, but only a simple wire:

module not_a_register(
  input in,
  output out
);

reg a;
always @(in) begin
  a <= in;
end

assign out = a;

endmodule

Also note that I have used the non-blocking assignment operator <= inside the always block, which is good practice when describing synchronous logic. You can read more about it here.

Upvotes: 4

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