CODEWITHSUNDEEP
vhdlfpgaintel-fpga
Deddy
Deddy

Reputation: 169

Shift unit in VHDL

As part of an alu design for a FPGA course I need to build a Shift unit capable of doing left shift and right arithmetic shift.

I wrote some VHDL code, simulated it in ModelSim and it worked fine. The next step was to compile it for an FPGA (ALTERA DE1). Now all the other operations of the ALU works fine but not the shift unit. For opcodes related to shift the output stays equals to the input.

entity Shift is
    generic (
        N : integer := 8 );
    port (
        A,B:in std_logic_vector(N-1 downto 0);
        OP: in std_logic_vector(2 downto 0);
        Enable: in std_logic;
        shiftedA:out std_logic_vector(N-1 downto 0));
end Shift;

architecture rtl of Shift is
begin
    shift_process: process (Enable,op,A,B)
        variable TempVec : std_logic_vector(N-1 downto 0) ;--:= (others => '0');
        variable inVector : std_logic_vector(N-1 downto 0);
        variable bitNum : Integer;
    begin
        inVector:=A;
        TempVec:=A;
        bitNum := conv_integer(B);
        test <= "00000000";
        if Enable = '1' then

            if OP = "100" then
                for i in 1 to bitNum loop
                    TempVec := TempVec(N-2 downto 0) & "0";
                end loop ;

            elsif OP = "101" then
                for j in 1 to bitNum loop
                    TempVec := A(N-1) & TempVec(N-1 downto 1);
                end loop;
            else
                TempVec := (others => '0');
            end if;
        else
            TempVec := (others => '0');
        end if;
        shiftedA <= TempVec;
    end process;
end rtl;

What am I doing wrong?

Upvotes: 1

Views: 588

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

Loops, like for i in 1 to bitNum loop are unrolled in synthesis for implementation as a circuit, but in this case the end condition for the loop is dependent on data, since bitNum is conv_integer(B), so conversion into hardware is a problem. Simulators can handle such constructions, since they do not convert into a circuit.

There is probably a synthesis warning telling this, so check the warnings, since some are actually relevant.

Telling more will spoil a good exercise... ;-)

Upvotes: 4

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