CODEWITHSUNDEEP
vhdlfpga
Yaro
Yaro

Reputation: 495

Module without an EN - VHDL

I've a module that when I don't use it, it must go to reset state so I don't need a moduleEN.

So, a module like this:

process(clock, reset)
            begin
                if reset = '0' then

                elsif rising_edge(clock) then

                end if;

It's correct for a synthesizer?

Or it's better:

process(clock, reset)
            begin
                if reset = '0' then

                elsif rising_edge(clock) then
                   if moduleEN = '1' then
                   end if;
                end if;

But with moduleEN costantly tied to high.

Upvotes: 2

Views: 72

Answers (1)

jpa
jpa

Reputation: 12176

It is perfectly ok to have a component without moduleEN signal. In fact, most of the modules I have seen do not have an enable signal.

However, if you plan to reset a submodule in runtime, it is more reliable to use a synchronous reset signal:

        process(clock, reset)
        begin
            if rising_edge(clock) then
               if reset = '0' then
                    ... reset logic ...
               else
                    ... normal logic ...
               end if;
           end if;
        end process;

This ensures that the module leaves the reset state cleanly. Otherwise the clock edge occurring close to the reset signal being deasserted could cause undefined behaviour.

Using asynchronous reset here is possible, but it will usually require specifying manual constraints to the timing analyzer to verify correct behaviour.

Upvotes: 2

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