CODEWITHSUNDEEP
vhdl
Gustavo Amgarten
Gustavo Amgarten

Reputation: 396

VHDL downto incorrect MSB

I have the following input signal:

addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);

As far as I know, this means that addr(9) is the most significant bit. But when run a simulation and assign, say, 128 to it, I get the following:

0(9) 0(8) 0(7) 0(6) 0(5) 0(4) 0(3) 1(2) 0(1) 0(0)

Meaning that the most significant bit is actually addr(0).

The assignment is done through simulation via vector waveform, in Quartus 9.1. I assign an arbitrary value to it.

Here is part of the .vhd file, where I use this:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

ENTITY ram_256x4B IS
PORT(clk, wr_en : IN STD_LOGIC; -- clock, write control signal
    addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); -- read and write addresses
    d : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- data to be written
    q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); -- memory read output
END ram_256x4B;

ARCHITECTURE comportamental OF ram_256x4B IS

SIGNAL addr_validation_bits : STD_LOGIC;

BEGIN
addr_validation_bits <= addr(9) & addr(8);

END comportamental;

If the valued of addr is 2, I expect addr(9) and addr(8) to be both 0, but instead they are 0 and 1, respectively.

Upvotes: 0

Views: 495

Answers (1)

Paebbels
Paebbels

Reputation: 16231

This assigns a STD_LOGIC_VECTOR with 128.

architecture ...
  signal addr : STD_LOGIC_VECTOR(9 downto 0);
begin
  addr <= std_logic_vector(to_unsigned(128, addr'length));
end;

addr(7) is '1', all other bits are '0'.

Upvotes: 1

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