CODEWITHSUNDEEP
vhdl
Mech
Mech

Reputation: 85

VHDL - Does not match a standard flipflop

Im trying to program something pretty easy with "VHDL". But Im stuck with it for a few hours already and I cant find a way to make it work.

Im trying to find a way to use the same signal in different process or combine them into one process. Using a signal in different processes is not possible and if I combine them into one process I get the error "Does not match a standard flipflop". I hope anyone here can help me out and say how I can fix this.

Example code;

process(scan_ready,rc5_ready) 
variable welkescan : std_logic_vector(1 downto 0);
begin
    if (scan_ready' event and scan_ready = '0') and not((rc5_ready' event and rc5_ready = '0')) then
      welkescan := "01";
      visualisatiegebruikt <= "0001";
      visualisatiecode <= scan_code;
    elsif (rc5_ready' event and rc5_ready = '0') and not((scan_ready' event and scan_ready = '0')) then
      welkescan := "10";
      visualisatiegebruikt <= "0010";
      visualisatiecode <= scan_con;
    else
      welkescan := "00";
    end if;

    if ((welkescan = "01" and scan_code = "01110010") or (welkescan = "10" and scan_code = "00100001")) and (pwm_on /= "11111100") then
      pwm_on <= pwm_on +  28;
      visualisatiepwm <= visualisatiepwm + "0001";
    elsif ((welkescan = "01" and scan_code = "01110101") or (welkescan = "10" and scan_code = "00100000")) and (pwm_on /= "00000000") then
      pwm_on <= pwm_on - 28;
      visualisatiepwm <= visualisatiepwm - "0001";
    end if;
end process;

What I also tried Code example:

process(scan_ready)
begin
    if scan_ready' event and scan_ready = '0' then
        visualisatie <= "0001"; -- 1 op display => toetsenbord
        scanwaarde(3 downto 0) <= scan_code(3 downto 0);
        scanwaarde(7 downto 4) <= scan_code(7 downto 4);
        if scan_code = "01110010" and pwmaansturen /= "11111100" then 
            pwmaansturen <= pwmaansturen +  28;
            visualisatiepwm <= visualisatie + "0001";
        elsif scan_code = "01110101" and pwmaansturen /= "00000000" then
            pwmaansturen <= pwmaansturen - 28;
            visualisatiepwm <= visualisatie - "0001";
        elsif scan_code = "01110100" then
            pwmaansturen <= "11111100";
            visualisatiepwm <= "1001";
        elsif scan_code = "01101011" then
            pwmaansturen <= "00000000";
            visualisatiepwm <= "0000";
        end if;
    end if;
end process;    

process(rc5_ready) 
    begin

    if rc5_ready' event and rc5_ready = '0' then
        visualisatie <= "0010"; -- 2 op display => afstandsbediening
        scanwaarde(3 downto 0) <= scan_con(3 downto 0);
        scanwaarde(7 downto 4) <= scan_con(7 downto 4);
        if scan_con = "00100001" and pwmaansturen /= "11111100" then 
            pwmaansturen <= pwmaansturen + 28;
            visualisatiepwm <= visualisatie + "0001";
        elsif scan_con = "00100000" and pwmaansturen /= "00000000" then 
            pwmaansturen <= pwmaansturen - 28;
            visualisatiepwm <= visualisatie - "0001";
        elsif scan_con = "00010110" then
            pwmaansturen <= "11111100";
            visualisatiepwm <= "1001";
        elsif scan_con = "00010111" then
            pwmaansturen <= "00000000";
            visualisatiepwm <= "0000";
        end if;
    end if;
end process;

I hope that someone can help me. Greetings.

Upvotes: 1

Views: 3432

Answers (1)

Paebbels
Paebbels

Reputation: 16231

This code has multiple issues.

First off all this code is not synthesizable. Using 'hardware description languages', which were made for simulation, for real hardware description and synthesis requires the designer to use several coding patterns so the tools can transform it into netlists and gates.

Main reasons for unsynthesizable code:

  1. You can not AND two clock events. When should this condition be true?
  2. You can not use not(clock'event ...).

Other hints and questions:

  • Why are you using falling edge events?
    Common designs use rising edge clock events. Not every platform has builtin support for falling edge flip flops.
  • Are scan_ready and rc5_ready two clock signals?
    • If yes: You build a design with multiple clock domains, which requires proper clock synchronization circuits and other staff to eliminate several faults in your design.
    • If no: Using rising/falling edge detection on non clock signals is not recommended. This would mean your design is asynchronous to your system clock, which also requires cross-clock circuits.

Upvotes: 1

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