CODEWITHSUNDEEP
vhdl
JakkeFire
JakkeFire

Reputation: 99

VHDL bidirectional bus mismatch

i have a module with 16bit inout bus. In my top level entity i only want to connect 4 of them (also inout bidirectional). Connecting them directly results in an error ofcourse

port map( IO16bit => IO4bit )

so i connected the m through an internal signal

signal temp : std_logic_vector (15 downto 0);
port map(IO16bit => temp);
IO4bit <= temp(3 downto 0);

but now i get the error: Tri-state nodes do not directly drive top-level pins and converted fanout into an OR gate

i lost the bidirectionality here. How can i solve this ?

Upvotes: 2

Views: 190

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

You can use a range in the port map, and then connect the remaining to a dummy like:

signal dummy : std_logic_vector(15 downto 4) := (others => 'Z');
...
port map(
  IO16bit( 3 downto 0) => IO4bit,
  IO16bit(15 downto 4) => dummy,
...

That will compile for simulation, but you have to check that your synthesis tool of choice can also accept the construction, and handle it correctly. It is often a problem to have internal inout ports in a synthesizable design.

Upvotes: 1

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