Reset output after run

Question

I'm working on a small project to learn VHDL. Currently I'm working on a BCD converter (converting a binary to its BCD number).

But I got stuck when implementing the testbench. It doesn't reset the output after the patterns got applied.

My VHDL code of the entity:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bcd_mod is
        port (
                entry: in std_logic_vector(16 downto 0);
                outp: out std_logic_vector(20 downto 0)
        );
end bcd_mod;

architecture calculate of bcd_mod is

begin
        process(entry)
                variable outp_cp : std_logic_vector(20 downto 0) := (others => '0');
                variable place : integer := 1;
                variable digit : integer := 0;
                variable number : integer := 0;

                begin

                        for i in 16 downto 0 loop
                                case entry(i) is
                                        when '0' => null;
                                        when '1' => number := number + (2**i);
                                        when others => null;
                                end case;
                        end loop;

                        if number > 99999 then
                                outp_cp(20) := '1';
                        else
                                while (number > 0) loop
                                        digit := number mod 10;

                                        if place = 1 then
                                                outp_cp(3 downto 0) := std_logic_vector(to_unsigned(digit, 4));
                                        elsif place = 2 then
                                                outp_cp(7 downto 4) := std_logic_vector(to_unsigned(digit, 4));
                                        elsif place = 3 then
                                                outp_cp(11 downto 8) := std_logic_vector(to_unsigned(digit, 4));
                                        elsif place = 4 then
                                                outp_cp(15 downto 12) := std_logic_vector(to_unsigned(digit, 4));
                                        else
                                                outp_cp(19 downto 16) := std_logic_vector(to_unsigned(digit, 4));
                                        end if;

                                        number := number - digit;
                                        number := number / 10;
                                        place := place + 1;
                                end loop;
                        end if;

                        outp <= outp_cp;
                        outp_cp := (others => '0');

        end process;

end calculate;

My testbench for the code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bcd_mod_testbench is
end bcd_mod_testbench;

architecture calculate of bcd_mod_testbench is
        component bmt
                port(entry : in std_logic_vector(16 downto 0); outp : out std_logic_vector(20 downto 0));
        end component;

        for bmt_0: bmt use entity work.bcd_mod;
                signal entry : std_logic_vector(16 downto 0);
                signal outp : std_logic_vector(20 downto 0);
                begin

        bmt_0: bmt port map (entry => entry, outp => outp);

        process
                type pattern_type is record
                        entry : std_logic_vector(16 downto 0);
                        outp : std_logic_vector(20 downto 0);
                end record;

                type pattern_array is array (natural range <>) of pattern_type;
                constant patterns : pattern_array :=
                (("00000110111101101", "000000011010101100101"),
                 ("00000000000000011", "000000000000000000011"),
                 ("00000000000011011", "000000000000000100111"));
                begin

                for i in patterns'range loop

                        entry <= patterns(i).entry;

                        wait for 1 ns;

                        assert outp = patterns(i).outp
                        report "Wrong BCD number." severity error;
                end loop;

                assert false report "End of test." severity note;
                wait;
        end process;
end calculate;

And here's the output in GTKWave. You can see here, that after running the code with a big number, the following numbers start where the number before ends.

(clickable)

Hope to get any tips to solve this problem.

Answer 1

Your problem is in the unlabeled process in bcd_mod. You aren't initializing place to 1 on each new entry:

architecture calculate of bcd_mod is

begin
unlabeled:
    process(entry)
        variable outp_cp:  std_logic_vector(20 downto 0) := (others => '0');
        variable place:  integer := 1;
        variable digit:  integer := 0;
        variable number:  integer := 0;
    begin
        place := 1;   -- ADDED
        for i in 16 downto 0 loop

And the problem becomes readily apparent if you look at the binary values, which I did with report statments in your testbench:

architecture foo of bcd_mod_testbench is
    component bmt
        port (
            entry:  in  std_logic_vector(16 downto 0);
            outp:   out std_logic_vector(20 downto 0)
        );
    end component;
    for bmt_0: bmt use entity work.bcd_mod;
    signal entry:  std_logic_vector(16 downto 0);
    signal outp:   std_logic_vector(20 downto 0);

    function to_string(inp: std_logic_vector) return string is
        variable image_str: string (1 to inp'length);
        alias input_str:  std_logic_vector (1 to inp'length) is inp;
    begin
        for i in input_str'range loop
            image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
        end loop;
        return image_str;
    end;
 begin

bmt_0: 
    bmt 
        port map (
            entry => entry,
            outp => outp
        );

unlabeled:
    process
        type pattern_type is record
            entry:  std_logic_vector(16 downto 0);
            outp:  std_logic_vector(20 downto 0);
        end record;

        type pattern_array is array (natural range <>) of pattern_type;
        constant patterns:  pattern_array := (
             ("00000110111101101", "000000011010101100101"),
             ("00000000000000011", "000000000000000000011"),
             ("00000000000011011", "000000000000000100111")
        );
    begin
        for i in patterns'range loop
            entry <= patterns(i).entry;
            wait for 1 ns;
            assert outp = patterns(i).outp
            report "Wrong BCD number pattern (" & integer'image(i) & ")"
            severity error;
            report "entry = " & to_string(entry);
            report "outp = " & to_string(outp);
        end loop;
        assert false report "End of test." severity note;
        wait;
    end process;
end architecture;

Which gives:

bcd_mod_tb.vhdl:119:13:@1ns:(report note): entry = 00000110111101101
bcd_mod_tb.vhdl:120:13:@1ns:(report note): outp = 000000011010101100101
bcd_mod_tb.vhdl:116:13:@2ns:(assertion error): Wrong BCD number pattern (1)
bcd_mod_tb.vhdl:119:13:@2ns:(report note): entry = 00000000000000011
bcd_mod_tb.vhdl:120:13:@2ns:(report note): outp = 000110000000000000000
bcd_mod_tb.vhdl:116:13:@3ns:(assertion error): Wrong BCD number pattern (2)
bcd_mod_tb.vhdl:119:13:@3ns:(report note): entry = 00000000000011011
bcd_mod_tb.vhdl:120:13:@3ns:(report note): outp = 000100000000000000000
bcd_mod_tb.vhdl:122:9:@3ns:(assertion note): End of test.

And when place is initialized, no error:

bcd_mod_tb.vhdl:119:13:@1ns:(report note): entry = 00000110111101101
bcd_mod_tb.vhdl:120:13:@1ns:(report note): outp = 000000011010101100101
bcd_mod_tb.vhdl:119:13:@2ns:(report note): entry = 00000000000000011
bcd_mod_tb.vhdl:120:13:@2ns:(report note): outp = 000000000000000000011
bcd_mod_tb.vhdl:119:13:@3ns:(report note): entry = 00000000000011011
bcd_mod_tb.vhdl:120:13:@3ns:(report note): outp = 000000000000000100111
bcd_mod_tb.vhdl:122:9:@3ns:(assertion note): End of test.

The to_string function added to support a '93 compliant VHDL tool.

Answer 2

In VHDL, a variable retains it's value between process re-entry. Thus, when you enter the process for the number X"000003", all your variables still have the value they add at the end of the processing of X"003565".

A quick test shows that setting place to 1 at the start of the process fixes the problem:

process(entry)
    variable outp_cp : std_logic_vector(20 downto 0) := (others => '0');
    variable place : integer := 1;
    variable digit : integer := 0;
    variable number : integer := 0;
begin
    place := 1;

    ...