CODEWITHSUNDEEP
additionvhdloperands
Sonadrin
Sonadrin

Reputation: 3

"+ can not have such operands in this context." error ( VHDL CODE)

  • can not have such operands in this context

Can someone tell me what is wrong and how to fix it please?

I tried to search the problem on the internet, why can't I add to STD_LOGIC_VECTOR and I didn't find anything that explains right my problem. So here I am asking you guys what's the problem?

entity Modes is
    Port ( RST : in  STD_LOGIC;
           CLK_33MHZ : in  STD_LOGIC;
           BTN : in  STD_LOGIC;
           LED : out  STD_LOGIC);
end Modes;

architecture Behavioral of Modes is

 signal ledstatus : STD_LOGIC;
 signal mode : STD_LOGIC_VECTOR(1 downto 0);
 signal modestatus : STD_LOGIC_VECTOR (1 downto 0);

begin 

 process(CLK_33MHZ,RST)

 variable cnt : integer range 0 to 33000000;

begin

 if(RST = '1') then
    cnt := 0;
    mode <= "00";
    LED <= '0';
    ledstatus <= '0';
     elsif(rising_edge(CLK_33MHZ)) then
        if(BTN = '1') then
            elsif(mode = "11") then
                mode <= "00";
                else
                **mode <= mode + "01";** -- the problem in the code
            end if;
         if(mode = "00") then
            LED <= '0';
            elsif(mode = "01") then
                LED <= '1';
                 elsif(mode = "10") then
                if(cnt = 33000000) then
                   LED <= not ledstatus;
                else
                   cnt := cnt + 1;
                end if;
             elsif(mode = "11") then
                if(cnt = 330000) then
                   LED <= not ledstatus;
                else
                   cnt := cnt + 1;
                end if;
       end if;
 end if;
 LED <= ledstatus; 

 end process;

end Behavioral;

Upvotes: 0

Views: 13983

Answers (1)

NIM
NIM

Reputation: 111

A std_logic_vector is just a vector of bits - it isn't necessarily a number. The + operator has no meaning in this context.

You need to explicitly state that it is a number, in your case an unsigned number, and then convert it back to a std_logic_vector:

mode <= std_logic_vector(unsigned(mode) + 1);

When mode is equal to 3, adding 1 will make it wrap back round to 0.

There are plenty of other issues with your code but this will fix that immediate synthesis error.

Upvotes: 6

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