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asynchronousverilogreset
fat balls
fat balls

Reputation: 131

How should I go about resetting my reset signal in Verilog?

I have 2 always blocks, one that counts the number of clock cycles that have passed capable of asynchronous reset and another that triggers the reset signal on the negedge of some input signal.

always@(posedge clock or posedge reset)

begin: ClockCounter

if(reset == 1)
    begin
    clock_cnt = 1;  
    end
else
    begin
    clock_cnt = clock_cnt + 1;
    end
end

always@(negedge pulse_in)

begin: Receiver

negedge_cnt = negedge_cnt + 1;

reset = 1;

.......Code goes on

end
end module

What I want to do is set the reset signal to 0 once the clock_cnt has been reset to 1 so it can continue counting in the following clock cycle. If I try to insert a reset = 0; after clock_cnt = 1; I get an issue with multiple drivers to the same signal. Does anybody have any idea how to do this?

Upvotes: 1

Views: 4944

Answers (2)

fat balls
fat balls

Reputation: 131

My solution was

always@(posedge clock or posedge reset)

begin: ClockCounter

if(reset == 1)
    begin
    clock_cnt = 1;
    reset_flag = 1;
    end
else
    begin
    clock_cnt = clock_cnt + 1;
    reset_flag = 0;
    end
end

always@(negedge pulse_in or posedge reset_flag)
begin

reset = 1;

if(reset_flag == 1)
reset = 0;
end

Upvotes: 0

Unn
Unn

Reputation: 5098

Unless there is a really important reason to do so, and you have guaranteed glitchless combinational logic, you should not use asynchronous resets to clear registers. The typical approach would be to use a synchronous clear signal rather than use the asynchronous reset.

Heres what the code would look like:

always @(posedge clk or posedge reset) begin
  if (reset) begin // Note that you need to separate the asynchronous reset and synchronous clear logic (ie, dont do 'if (reset | clr)') 
    counter <= 1; // Use non-blocking assignment for clocked blocks
  end
  else begin
    if (clr) begin
      counter <= 1;
    end
    else begin
      counter <= counter + 1;
    end
  end
end

always @(posedge clk) begin // You need to synchronize your input pulse, Im assuming its synchronous to your clock, otherwise youll need a synchronizer
  if (prev_pulse_in & ~pulse_in) begin
    negedge_cnt <= negedge_cnt + 1;
    clr <= 1;
  end
  else begin
    clr <= 0;
  end
  prev_pulse_in <= pulse_in;
end

Upvotes: 1

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