CODEWITHSUNDEEP
verilogfpgaintel-fpga
西瓜籽
西瓜籽

Reputation: 21

How to realize "posedge asynchronous reset logic" in verilog?

i know high level async reset can be achieved like:

always@(posedge clk or posedge rst)
begin
  if (rst==1)

but how to realize posedge async reset, which means the moment reset edge coming up, the logic in always block reset immediately?

i wrote the logic below:

always@(posedge clk or posedge rst)
begin
  rst_pre<=rst;
  if(!rst_pre && rst) // to test if rst is posedge
      //execute reset logic here...

but the question is, the always block was triggered in a unexpected high frequency, i finally figured out that although there was only 1 posedge of rst, the always block was triggered by rst signal much more than 1 time. (tested using altera cyclone 10LP with quartus 18)

I think the method i used to achieve posedge async reset is not stable, can anyone tell me what can i do to solve this?

Upvotes: 0

Views: 2935

Answers (3)

Anusha Manoj
Anusha Manoj

Reputation: 19

What you are trying to achieve is a asynchronous reset. It can be posedge or negedge.

always@(posedge clk or posedge rst)
begin
   if (rst) 
      // do the reset
   else begin
      // your normal execution logic
   end
end

If you want to use negedge reset then you can use:

always@(posedge clk or negedge rst)
begin
   if (~rst) 
      // do the reset
   else begin
      // your normal execution logic
   end
end

Other than that, there is nothing complicated on reset. Both on these occasions, on posedge/negedge of rst, block will get triggered and it will do the reset.

Upvotes: 2

m4j0rt0m
m4j0rt0m

Reputation: 354

As soon as you include "posedge/negedge reset" in the sensitivy list, and the reset condition inside the always block has priority over the rest of the sequential logic, it is asynchronous:

always @ (posedge clk_i, posedge arst_i) begin
  if(arst_i) begin
    ...this condition has to be first
  end
  else begin
    ...normal sequential logic
  end
end

Use "posedge" for active-high reset, and "negedge" for active-low reset.

Extra note: Sometimes it is also useful to have a reset synchronizer. This synchronized "soft reset" should be included in the normal sequential logic and it would help to have everything synchronized with the clock. By doing this you would have a first asynchronous reset condition, and the last synchronized reset would avoid any metastabiliy problems regarding the asynchronous condition.

Upvotes: 1

Light
Light

Reputation: 1316

The very first code snippet which you call "high level async reset" logic is "posedge asynchronous reset logic".

The code snippet specified a active high asynchronous reset signal rst. "active high" + "asynchronous" means signals generated by this always block are reset immediately when rst asserts.

Upvotes: 1

Related Questions