CODEWITHSUNDEEP
vhdlactive-hdl
EquipDev
EquipDev

Reputation: 5931

How to do simple Aldec Active-HDL simulation with waveform using Tcl scripting?

Having a simple test bench like:

entity tb is
end entity;

architecture syn of tb is
  signal show : boolean;
begin
  show <= TRUE after 10 ns;
end architecture;

ModelSim GUI allows simulation and waveform viewing with a Tcl script in "all.do" with:

vlib pit
vcom -work pit tb.vhd
vsim pit.tb
add wave sim:/tb/show
run 20 ns

Where to do all.do in the ModelSim GUI console will make library, compile, load tb model, and show the waveform:

enter image description here

How to make a similar simple Tcl script for a similar simulation with Aldec Active-HDL simulator ?

Upvotes: 2

Views: 1784

Answers (1)

EquipDev
EquipDev

Reputation: 5931

Aldec Active-HDL documentation for Tcl use is pretty vague for how to use Tcl from the GUI, but enough time with trial and error gave a positive result.

It appears that it is required to create workspace with design, whereby a library for work is also created, and then design files can be compiled into the library.

The resulting Tcl script for Active-HDL is:

workspace create pit    # Create workspace namded "pit" and open this
design create -a pit .  # Create design named "pit" with "pit" library as work and add to workspace
acom $DSN/../tb.vhd     # Compile "tb.vhd" file with location relative to workspace
asim work.tb            # Load simulator from work library
add wave /tb/show       # Add wave "show" to waveform
run 20 ns               # Simulate 20 ns

Which will give the waveform:

enter image description here

Upvotes: 5

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