CODEWITHSUNDEEP
veriloghdl
archity
archity

Reputation: 612

Code to generate a periodic waveform always shows output as 0

I'm writing a Verilog program which would repeatedly run and change the value of the variable clk from 0 to 1, back to 0 and so on, running infinite times. Here's the code of the module:

module FirstQuestion(
output clk
);
reg clk;

initial
begin
    while (1)
    begin
        clk = 0;
        #10
        clk = 1;
    end
end    
endmodule

However, the output waveform is just showing 0 as the output. Can the mistake be just pointed out and corrected? Here is the code for testbench:

module FirstQuestion_tb;

wire ty;

FirstQuestion mygate (.clk(ty));
integer i;
initial 
begin
    $monitor(ty);
    //for(i=0; i<10; i=i+1);
end
endmodule

Upvotes: 0

Views: 1826

Answers (2)

Shankhadeep Mukerji
Shankhadeep Mukerji

Reputation: 668

You can also define a clock generator with a CLK_PERIOD = 10 ns, like

`timescale 1ns/1ps

`define CLK_PERIOD 10

....

    initial
    begin
       clk = 0;
       forever #CLK_PERIOD clk = ~clk;
    end

Upvotes: 3

toolic
toolic

Reputation: 62121

The problem is that you set clk=1 at the end of the while loop, then immediately set clk=0 at the beginning of the loop without any delay between. So, waves show that clk=0 always.

You need to add another delay:

initial
begin
    while(1)
    begin
        #10
        clk = 0;
        #10
        clk = 1;
    end
end

Upvotes: 2

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