CODEWITHSUNDEEP
verilog
you_know_who
you_know_who

Reputation: 55

Generate custom waveform in verilog

I am trying to generate waveform in verilog using the code below but the result aren't as expected.

initial begin
    d = 1'b0;
#8  d <= 1'b1;
#15 d <= 1'b0;
end

Its initial value is 0(OK), at t=8, its 1(OK) but at t=23, its 0. Instead i want it to be 0 at t=15 relative to t=0 and not to t=8(i.e. previous statement).

Is there a way to do so? I have tried interchanging blocking and non-blocking assignments but no luck!

Upvotes: 4

Views: 610

Answers (2)

No one
No one

Reputation: 1

module top_module(
    input [2:0] vec,
    output [2:0] outy,
    output out0,
    output out1,
    output out2
);

    assign outy = vec;
    assign out0 = vec[0];
    assign out1 = vec[1];
    assign out2 = vec[2];

endmodule

Upvotes: -3

Matthew
Matthew

Reputation: 13987

You could do this:

initial fork
    d = 1'b0;
#8  d = 1'b1;
#15 d = 1'b0;
join

All the statements inside fork join will be executed concurrently.

Or you could do this:

initial     d = 1'b0;
initial  #8 d = 1'b1;
initial #15 d = 1'b0;

Clearly, the three initial blocks will be executed concurrently.

If you really wanted to schedule 3 events from procedural (sequential) code, then you could do this:

initial begin
  d  =     1'b0;
  d <=  #8 1'b1;
  d <= #15 1'b0;
end

This uses intra-assignment delays together with non-blocking assignments.

http://www.edaplayground.com/x/4MiS

Upvotes: 4

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