CODEWITHSUNDEEP
verilogwaveform
Victor Brunell
Victor Brunell

Reputation: 6418

Verilog Wave Forms

I need to build a waveform from the following code:

module HW7P1 (A1, A0, B1, B0, O);
        input A1, A0, B1, B0;
        output O;
        assign O = (!A1 & B1) | (!A1 & !A0 & B0) | (!A0 & B1 & B0);
endmodule

module counter (clr, clk, OC);
        input clr, clk;
        output reg [3:0] OC;

        initial begin
                OC = 0;
        end

        always @(posedge clk) begin
                if (clr == 0)
                        OC = 0;
                else
                        OC = OC + 1;
        end
endmodule

module test_bench ();

wire HW7P1A1, HW7P1A0, HW7P1B1, HW7P1B0, HW7P1O;
wire clr, clk;
wire [3:0] counterO;
reg osc;


initial begin
osc = 0;
end

always begin
#10 osc = ~osc;
end


assign clr=1;
assign clk=osc;
counter C1(clr, clk, counterO);

assign HW7P1A1 = counterO[3];
assign HW7P1A0 = counterO[2];
assign HW7P1B1 = counterO[1];
assign HW7P1B0 = counterO[0];

HW7P1 P1(HW7P1A1, HW7P1A0, HW7P1B1, HW7P1B0, HW7P1O);

endmodule

I'd like to use EDA playground to do this since I don't have Verilog simulation software installed on my computer. However, when I select the "open EPWave after run" option, nothing seems to happen after I hit run. Can someone please tell me what I'm doing wrong?

Upvotes: 1

Views: 11144

Answers (1)

Chiggs
Chiggs

Reputation: 2864

Firstly you need to end the simulation, otherwise the sim will just run forever and eventually the process will get killed. You can do this by adding a call to $finish:

#10000 $finish

Secondly you need to create a VCD. Once you've added the above code EDAPlayground will give you a helpful error message:

No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd"); $dumpvars;'?

So by adding the following code:

initial begin
  $dumpfile("dump.vcd");
  $dumpvars;
  #10000 $finish;
end

Your example code runs and is viewable in the waveform viewer: http://www.edaplayground.com/x/3v2

Upvotes: 7

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