CODEWITHSUNDEEP
verilogwaveform
PYPL
PYPL

Reputation: 1859

Changing freq of triangle waveform verilog

So I've already got my triangle waveforms, now i want to change the frequency of it, but i'm getting errors and i don't know what's the actual problem.

module sxoc(clk,res,out1,freq,count);
input  clk,res;
input [0:7]freq;
output [0:7]count;
output [0:7]out1;
reg [0:7]out1;
always @(posedge clk)
begin
    if (res)
    begin
        out1=8'b00000000;
        count=8'b00000000;
    end
    else
        count =count + 1;
        if (count == freq)
            if(out1<=256)
            begin
                out1=out1 + 1;
                count = 0;
            end
end
endmodule
module atam_test;
reg clk,res;
reg [0:7]freq;
wire [0:7]count;
wire [0:7]out1;
sxoc sxoc1(clk,res,out1,freq,count);
always #2 clk=~clk;
initial 
begin
clk=0;res=1;freq=8'b00000011;
#5 res=0;
end
initial #5000 $finish;
endmodule

Compilation errors

Upvotes: 1

Views: 424

Answers (1)

toolic
toolic

Reputation: 62121

Procedural assignments (in an always block) can only be made to a reg. Change:

output [0:7]count;

to:

output reg [0:7]count;

Upvotes: 1

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