CODEWITHSUNDEEP
verilogfpgasystem-verilogxilinxvivado
jwanga
jwanga

Reputation: 4256

Error synthesizing hierarchical names in vivado

Using Vivado 2015.1, I'm attempting to use a hierarchical name to access an object on the top level module of my design. The simulation runs fine but I receive the following synthesis error:

[Synth 8-660] unable to resolve 'top' ["child.sv":3]

module top()
    logic foo;
endmodule

module child()
    always(bar) begin
        logic top.foo <= bar;
    end
endmodule

Any Ideas?

Upvotes: 4

Views: 5873

Answers (2)

None
None

Reputation: 2433

Supported in Vivado 2019.1 UG901 enter image description here

Upvotes: 1

jwanga
jwanga

Reputation: 4256

So, It turns out that hierarchical names are not supported in Vivado synthesis.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug901-vivado-synthesis.pdf

Upvotes: 2

Related Questions