CODEWITHSUNDEEP
verilog
Gokel Thottempudi
Gokel Thottempudi

Reputation: 93

How to send only sparse memory bits to another module

I am having a buffer which contains 512 bits and I want to send only the sparse bits to other module in Verilog.

My memory is like reg[511:0]mem[68]. The other module can accept 32 bits at a time and it does not want all the 512 bits in the memory and needs only sparse bits. How can i send these sparse bits in Verilog?

Upvotes: 0

Views: 502

Answers (1)

t.c.
t.c.

Reputation: 1

If your sparse bits' place are fixed (fixed memory address and fixed data bit address), you can just fetch each bit, and pack them into a bus,e.g.:

wire [511:0] data_mem0 = mem[x1];
wire [511:0] data_mem1 = mem[x2]; 
wire [31:0] sparse_bits = {data_mem0[7:0],data_mem1[7:0],data_mem0[511:504],data_mem1[511:504]};

if the sparse bits' place are not fixed, then things will become complicated. You'd better wrap your memory with a simple memory accessing bus interface. Through the interface, get all your spare bits, then pack them into a 32-bit bus. Now you can send this 32-bit signal to another module.

Simple memory bus interface:

module mem_if(
  addr,
  rw,
  din,
  dout,
  clk,
  rst_
);
  input  [6:0]   addr;
  input          rw;
  input  [511:0] din;
  output [511:0] dout;
  input          clk;
  input          rst_;

Upvotes: 0

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