CODEWITHSUNDEEP
vhdl
Learner
Learner

Reputation: 1

Error for if statement condition in adder/subtractor

I am new to the VHDL language, so please bear with me and please help me out.

I have written code for a addition/subtraction unit which will operate on signed integer but at the "if else" part in the last, the compiler is giving an error. 

library ieee;  
use ieee.std_logic_1164.all;  
use ieee.numeric_std.all;
entity adder is  
port(A,B : in  std_logic_vector(3 downto 0);  
     SUM : out std_logic_vector(3 downto 0);  
     mode: in  std_logic_vector(0 downto 0));
end adder; 


architecture behave of adder is  

component xorgate is
port( p,q: in  std_logic_vector(3 downto 0);
        r: out std_logic_vector(3 downto 0));
end component;

signal a1,b1,sum1,output1,mode1:integer;
signal tmp: std_logic_vector(3 downto 0);
variable output: std_logic_vector(3 downto 0);


begin
u1: xorgate  port map (B, mode, output);
output1 <= to_integer(signed (output));
a1      <= to_integer(signed(A));
b1      <= to_integer(signed(B));
mode1   <= to_integer(signed(mode));

process(a1,output1,b1,tmp,mode1)
begin
if ( mode1 <= '1') then
sum1 <= a1 + output1 ;
else
sum1 <= a1 + b1;
end if; 

tmp <= std_logic_vector(to_signed(sum1,4));
SUM <= tmp( 3 downto 0);
end process;
end behave;

XST Error Message:

ERROR: HDLCompiler:1731 - "E:\XILINX PROGRAM\FULLADD\FULLADD.vhd" Line 31: found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<="
ERROR: HDLCompiler:854 - "E:\XILINX PROGRAM\FULLADD\FULLADD.vhd" Line 11: Unit ignored due to previous errors.

Upvotes: 0

Views: 418

Answers (3)

user1818839
user1818839

Reputation:

The puzzle is probably why the error message is about failure to find an overloaded operator

'1' has at least two definitions, first as a character literal, then as a bit literal. Neither of these have a <= operator comparing them with type Integer, and that's why the compiler gave up.

If you had used an integer literal 1 instead, the compiler could have found a <= operator easily... so if mode1 <= '1' then would work.

Alternatively, you could write your own <= operator accepting inputs of these two types and returning a boolean : 

function "<=" (a : Integer; b : Bit) return Boolean is ...

While it would work, it would also deserve a slap on the wrist!

Upvotes: 0

Morten Zilmer
Morten Zilmer

Reputation: 15924

The <= operator in mode1 <= '1' is less-than-or-equal compare of integer with '1', which have no definition, thus the found '0' definitions of operator "<=". Change '1' to simply the integer literal1`.

Other issues with the code are listed below.

The ´variable output: ...´ must be signal output: when output is used as actual for in port map for xorgate. In typical design you don't have variables in the declaration section, between begin and end, of an architecture.

Length of mode is only 1 std_logic (bit), but actual for mode in xorgate port map, which is q in xorgate, is 4 bits. You probably meant to make mode as 3 downto 0 in the port declaration of adder, since compare like mode1 <= 1 will be trivial true if mode is 1 bit.

The intermediate integer signals named *1 and other signal are actually not required if the process uses signed additions from numeric_std package like:

process(A, B, mode, output) is
begin
  if signed(mode) <= 1 then
    SUM <= std_logic_vector(signed(A) + signed(output));
  else
    SUM <= std_logic_vector(signed(A) + signed(B));
  end if;
end process;

And this can even be reduced to the below, with only output as intermediate signal:

SUM <= std_logic_vector(signed(A) + signed(output)) when (signed(mode) <= 1)
       else std_logic_vector(signed(A) + signed(B));

Finally, if mode is to be treaded like unsigned, then replace with unsigned(mode), since unsigned is also defined in the numeric_std package.

Upvotes: 0

scary_jeff
scary_jeff

Reputation: 4374

Line 31: if ( mode1 <= '1') then

you meant: if ( mode1 = 1) then

Line 11: This just means that because of the previous error, the compiler 'gave up'.

Upvotes: 1

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