CODEWITHSUNDEEP
vhdlfpgaquartus
Federico Ponti
Federico Ponti

Reputation: 95

Variable or signal in vhdl for shared value between different process

I need to share a value (a real) between two process, but when I try to run my code, quartus gives me an error.

library IEEE;
USE ieee.std_logic_1164.all; 
USE ieee.std_logic_arith.all; 
USE ieee.std_logic_unsigned.all; 
use IEEE.MATH_REAL.ALL;

entity de0nano is
port (
 CLOCK_50      : in  std_logic;
KEY           : in  std_logic_vector(1 downto 0);
 SW            : in  std_logic_vector(3 downto 0);
 LED           : out std_logic_vector(7 downto 0);
 GPIO           : inout std_logic_vector(35 downto 0)


  );
end de0nano;

architecture struct of de0nano is
--declarations
signal   PN                 :  real :=0.0 ;
signal   PR                 :  real :=0.0 ;
signal   RC             :  integer :=1;
signal   NC             :  integer :=1;
signal   BET                :  integer :=1;


begin
count : process (CLOCK_50, GPIO)
begin 
 --A <= KEY(0);
 GPIO(24) <= '1';
--functional coding
LED <= "00011000";
 if (pn > pr) then
GPIO(26) <= '1';
LED <= "00000001";
else
GPIO(26) <= '0';                    
    end if;
 if (pn = pr) then
GPIO(26) <= '1';
LED <= "00000010";
else
GPIO(26) <= '0';                    
end if;
 if (pn < pr) then
GPIO(26) <= '1';
LED <= "00000011";
else
GPIO(26) <= '0';                    
end if;

end process;

probabilityController : process (CLOCK_50, KEY)
begin
--stato iniziale
if((RC + NC + BET)=1) then
pr <= 0.5;
pn <= 0.5;
end if;
--sequenza rossi consecutivi
if(RC>0) then
pr <= (5)**RC;
pn <= 1- (5)**RC;
end if;
--sequenza neri consecutivi
if(NC>0) then
pr <= (5)**NC;
pn <= 1- (5)**NC;
end if;

end process;

betController : process (CLOCK_50)
begin

end process;

colorController : process (CLOCK_50, KEY)
begin
if(KEY(0)='1') then
NC<=0;
RC <= RC+1;
end if;

if(KEY(1)='1') then
RC<=0;
NC <= NC+1;
end if;


end process;

end str

How can I operate in the same signal/variable from two different processes?

Upvotes: 0

Views: 3941

Answers (1)

Renaud Pacalet
Renaud Pacalet

Reputation: 29040

VHDL is a hardware description language. A VHDL description can be simulated (executed a bit like you do with most programming languages) or synthesized (transformed in a network of interconnected simple hardware elements). Some tools are pure simulators (Mentor Graphics Modelsim, Cadence ncsim...), others are pure synthesizers (Mentor Graphics Precision RTL, Cadence RTL compiler...) and others can do both. Quartus pertains to the last category. So, the first thing to do is to decide whether you want to simulate, synthesize or both.

In case you want to simulate you must fix three errors:

  • the position of your signal declaration,
  • the way you assign it (:=) which is the variable assignment operator, not the signal assignment (<=)
  • and the fact that you drive it from two processes while it is of an unresolved type (real). See this other answer for resolved / unresolved VHDL types.

Your code could then look like this (but as I do not know what you are trying to do, it is probably not what you want):

architecture V1 of AOI is
    Signal foobar : real := 0.0;
begin
    OneTwo : process (clk)
    Begin
         Foobar <= foobar + 2.0;
    End process;
end V1;

If you want to synthesize you will have to fix a few more problems:

  • You are using the real type which is the floating point VHDL type. This is not synthesizable by the synthesizers I know. Indeed, what would you expect the synthesizer to do? Instantiate a complete floating point unit? What brand? So, you will have to replace real by some other type (integers, bit vectors...).
  • You are assigning your signal on both edges of what I believe is your clock (clk). This is probably not what you want.
  • You are initializing the signal at declaration time. This is usually not synthesizable by the synthesizers I know. In fact this initialization time has a clear meaning for simulation: it is the beginning of the simulation. But what about hardware? What is the beginning of a piece of hardware? Manufacturing? Power up? So, if you want the signal to be initialized at some point you will have to add a hardware reset, driven by a reset input.

All in all you could have something like:

architecture V1 of AOI is
    Signal foobar : natural range 0 to 255;
begin
    OneTwo : process (clk)
    Begin
         if rising_edge(clk) then
              if reset = '1' then
                  foobar <= 0;
              else
                  foobar <= foobar + 2;
              end if;
         end if;
    End process;
end V1;

Notes:

  • VHDL is case insensitive but you should try to be consistent, it will help you.
  • You should probably take a VHDL course or read a VHDL primer before trying to use the language. It is radically different from the programming languages you already know. Hardware and software are pretty different worlds, even if they are strongly connected at the end.

Upvotes: 1

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