CODEWITHSUNDEEP
verilogdigital-logiciverilog
Scruffy Nerfherder
Scruffy Nerfherder

Reputation: 189

4Way Demultiplexer circuit using Verilog

I am struggling here on an assignment for my digital logic class. I have searched online for resources, but there is not much that has proven to be helpful. It seems that everyone has a different approach than what we are doing in class. There is no textbook either, just weekly handouts and this one is not very helpful either. I have e-mailed my instructor and no response. So basically, this is my last hope.

I need to build a 4way demultiplexer, however, it must be done by first building a 2way demultiplexer and then using three of those to create a four-way demultiplexer.

That is pretty much all the instruction we got. We were shown how to create a 4way multiplexer the same way - by first creating a 2way, and using that 3 times. So, I just sort of modified what we were shown there. But my out put is not quite right. I am getting a 'z' for every output.

enter image description here

the "exp0, exp1, exp2, exp3" is the expected output I should be getting.

2Way Demux 

module demux2way(outA, outB, in, sel);
    input in, sel;
    output outA, outB;
    wire s0, w0, w1;

    not(s0, sel);
    and(outA, w0, s0, in); 
    and(outB, w1, sel, in); 

endmodule

4way Demux

module demux4way(out0, out1, out2, out3, in, sel0, sel1);
   input in, sel0, sel1;
   output out0, out1, out2, out3;
   wire w0, w1;

   demux2way dmx0 (w0, w1, in, sel0);
   demux2way dmx1 (w0, sel1, out0, out1);
   demux2way dmx2 (w1, sel1, out2, out3);

endmodule

4Way Demux Testbench

module demux4way_tb();
    reg inA, selA, selB;
    wire outA, outB, outC, outD;
    reg exp0, exp1, exp2, exp3;

initial begin
    #0 selA=0; selB=0; inA=0; exp0=0; exp1=0; exp2=0; exp3=0; 
    #2 selB=1; exp0=0; exp1=0; exp2=0; exp3=0;
    #2 selA=1; selB=0; exp0=0; exp1=0; exp2=0; exp3=0;
    #2 inA=1; selA=0; exp0=1; exp1=0; exp2=0; exp3=0;
    #2 selB=1; exp0=0; exp1=1; exp2=0; exp3=0;
    #2 selA = 1; selB=0; exp0=0; exp1=0; exp2=1; exp3=0;
    #2 selB=1; exp0=0; exp1=0; exp2=0; exp3=1;
    #10 $finish; //End the simulation

end

initial begin
    $monitor ("time=%4d: sel0=%b sel1=%b in=%b out0=%b out1=%b 
    out2=%b out3=%b, exp0=%b exp1=%b exp2=%b exp3=%b",
    $time, selA, selB, inA, outA, outB, outC, outD, exp0, exp1, exp2, exp3);
end

demux4way demux01( .sel0(selA), .sel1(selB), .in(inA),  .out0(outA), .out1(outB), .out2(outC), .out3(outD));

endmodule

Upvotes: 1

Views: 930

Answers (1)

Unn
Unn

Reputation: 5098

You mixed up the order of ports in your demux4way module. You should use the style you used in your testbench of module instantiation to avoid this problem:

module demux4way(out0, out1, out2, out3, in, sel0, sel1);
   input in, sel0, sel1;
   output out0, out1, out2, out3;
   wire w0, w1;

   demux2way dmx0 (.outA(w0), .outB(w1), .in(in), .sel(sel0));
   demux2way dmx1 (.in(w0), .sel(sel1), .outA(out0), .outB(out1)); // Was .outA(w0), .outB(sel1), .in(out0), .sel(out1)
   demux2way dmx2 (.in(w1), .sel(sel1), .outA(out2), .outB(out3)); // Was .outA(w1), .outB(sel1), .in(out2), .sel(out3)

endmodule

Also note that the wires w0 and w1 in your demux2way do nothing and should be removed.

Upvotes: 3

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