Suboptimal Timing Implementation Warning - F7 Multiplexer

Question

I'm attempting to create an I2C bus for testing as part of my attempt to program a DVI Ch7301c.

I'm supplying it with test data, however, when I try and transmit the data values hex 77, it throws this warning:

Pack:2574 - The F7 multiplexer symbol
   "I2C_Master/Mmux_bit_cnt[2]_DAT_WR[7]_Mux_45_o_2_f7" and its I1 input driver
   "I2C_Master/Mmux_bit_cnt[2]_DAT_WR[7]_Mux_45_o_3" were implemented
   suboptimally in the same slice component. The function generator could not be
   placed directly driving the F7 multiplexer. The design will exhibit
   suboptimal timing.

After narrowing it down, it seems to be thrown in the case statement, but only when sending the value value hex 77. Additionally, I can send the value hex 77 elsewhere in the case statement, just not in the when counter <= 3 What does this warning signify, and why does it appear to strike only the apparently random value of hex 77.

My code is below - I haven't added the code for the I2C_Master module as it doesn't appear to be responsible for the error.

Thanks very much!

David

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity I2CBus is
    PORT(
        SYSCLK_N : IN    STD_LOGIC;     --system 200MHz differential clock
        SYSCLK_P : IN    STD_LOGIC;
        BTN      : IN    STD_LOGIC;     -- to manually change reset

        SCL      : INOUT STD_LOGIC;     --SCL & SDA lines
        SDA      : INOUT STD_LOGIC;
        SCL_cpy  : OUT   STD_LOGIC;     --SCL & SDA lines
        SDA_cpy  : OUT   STD_LOGIC
    );
end I2CBus;
architecture Behavioral of I2CBus is
    component IIC_Master is
        Generic(input_clock : integer;  --system clock
                bus_clock   : integer);
        Port(CLOCK   : in    STD_LOGIC;
             RESET_N : in    STD_LOGIC; --Active low
             ENA     : in    STD_LOGIC; --Enable active high
             ADR     : in    STD_LOGIC_VECTOR(6 downto 0); --target address
             RW      : in    STD_LOGIC; --read low, write high
             REG     : in    STD_LOGIC_VECTOR(7 downto 0); --target register
             DAT_WR  : in    STD_LOGIC_VECTOR(7 downto 0); --data to write to slave
             DAT_RD  : out   STD_LOGIC_VECTOR(7 downto 0); --data to read from slave
             BUSY    : out   STD_LOGIC; --high when busy
             SCL     : inout STD_LOGIC; --serial clock of i2C bus
             SDA     : inout STD_LOGIC; --serial data on bus
             ACK_ERR : buffer STD_LOGIC); --flag if wrong ack from slave
    end component;
    component DCM
        port(
            SYSCLK_P : in  std_logic;   -- Clock in ports 200MHz differential
            SYSCLK_N : in  std_logic;
            -- Clock out ports
            SYSCLK   : out std_logic    --300 MHz clock out
        );
    end component;
    -----Clock signals -------------
    signal sysclk      : std_logic;     --300 mhz system clock
    ----Internal Signals------------
    signal ack_err     : std_logic;     --error from dvi slave
    signal busy        : std_logic;     --is I2C master busy?
    signal slave_dout  : std_logic_vector(7 downto 0); --data out from slave
    signal reset_n     : std_logic;     --reset low
    signal i2c_wr      : STD_LOGIC;     --R/W value to send
    signal i2c_wdata   : STD_LOGIC_VECTOR(7 downto 0); --data to send
    signal i2c_regdata : STD_LOGIC_VECTOR(7 downto 0); --target register
begin
    --------Instantiate DCM------------------
    DCM_Clks : DCM
        port map(                       -- Clock in ports
            SYSCLK_P => SYSCLK_P,       --Map input clocks directly
            SYSCLK_N => SYSCLK_N,
            -- Clock out ports
            SYSCLK   => SYSCLK);
    ------------------------------------------
    ---Instantiate I2C Bus Driver-------------
    I2C_Master : IIC_Master
        Generic map(input_clock => 300000000, --system clock
                    bus_clock   => 300000000 / 16)
        Port map(CLOCK   => sysclk,     --300 MHz system clock (runs at 1/8th that)
                 RESET_N => RESET_N,    --get reset from dvi initialiser
                 ENA     => '1',        --enable signal from above
                 ADR     => "1010110",  --target DVI address straight from input
                 RW      => i2c_wr,     --get R/W from initialiser 
                 DAT_WR  => i2c_wdata,  --data to write from initialiser
                 REG     => i2c_regdata, -- target register
                 DAT_RD  => open,       --data read from DVI device (inactive at present)
                 BUSY    => busy,       --I2C finished writing
                 SCL     => SCL,        -- output straight to SCL
                 SDA     => SDA,        -- output straight to SDA
                 ACK_ERR => ack_err);   --flag if wrong ack from slave
    --------------------------------------------
    reset_proc : process(sysclk)
        variable counter : integer range 0 to 4;
        variable edge    : boolean; --used to detect busy falling edge
    begin
        if rising_edge(sysclk) then
            if busy = '1' then
                edge := true; --next '0' will be an edge
            end if;
            if busy = '0' and edge and counter < 3 then
                counter := counter + 1; --increment counter
                edge    := false; --reset edge
            end if;
            case counter is
                when 0 =>
                    i2c_wr      <= '0'; --set to write
                    i2c_regdata <= x"AA"; --send new target register
                    i2c_wdata   <= x"99"; --send new write data
                when 1 =>
                    i2c_regdata <= x"FF";
                    i2c_wdata   <= x"55";
                when 2 =>
                    i2c_regdata <= x"BB";
                    i2c_wdata   <= x"77"; --WARNING occurs here when sending x"77"
                when others => null;
            end case;
        end if;
    end process;
    reset_n <= not BTN;                 --reset process;
    SDA_cpy <= SDA;                     --copy SDA & SCL to observable pins
    SCL_cpy <= SCL;
end Behavioral;

Answer 1

Have a look into the Spartan-6 CLB Guide and you'll find two F7 mux and a F8 mux.

The LUT of your FPGA can implement every boolean 6-input function ("F6"). If a 7-input function is needed, two LUT6 and a F7MUX are used to map this function into the CLB.

An 8-input function needs four LUT6 two F7MUX and one F8MUX.

The timing is slower than a LUT6 but faster than a LUT tree.

The warning is emitted to remind you to describe functionality with a low input count. If you change your code or some constants, it's possible that optimizations could not find a compact 6 input function anymore.