CODEWITHSUNDEEP
verilogcircuitdigital-logiciverilog
Scruffy Nerfherder
Scruffy Nerfherder

Reputation: 189

Ring Counter in Verilog

I need to modify this ring counter to shift from the most to least significant bit and then resets back to the most significant bit. The output should look like this:

100000 
010000 
001000 
000100  
000010 
000001 
100000

Ring Counter

module ringcounter(clk, rst, count);  
    input clk, rst; 
    output [5:0] count; 
    wire clk, rst; 
    reg [5:0] count = 6'b1;  
    // Respond to the positive-going pulse edge     
    always @ ( posedge clk ) 
        begin   
        if ( ~rst )   
            begin     
            count <= count << 1;    
            count[0] <= count[5];   
        end 
    end  
    // Respond to the positive-going reset signal 
    always @ ( posedge rst ) 
    begin   
        count <= 6'b1; 
    end  
endmodule

Ring Counter Testbench 

module ringcounter_tb();  
    reg clk = 0, rst = 0; 
    wire [5:0] count;  
    always #1 clk = !clk; // Create a clock pulse  

    initial begin   
    $monitor("At time %4t, count = %b", $time, count );  
        #20 rst = 1;   
        #1  rst = 0;
        #20 $finish; 
    end  

    ringcounter cntr01 ( .clk(clk), .rst(rst), .count(count) );  
endmodule

I am still very new to digital logic, so please bear with me. I am just a little confused as to how I could modify this ring-counter. Any kind of help, or explanation as to how exactly this would work, would be greatly appreciated.

Upvotes: 0

Views: 3764

Answers (2)

sharvil111
sharvil111

Reputation: 4381

The question is not very clear here. But a couple of things to be modified.

Firstly, never use same variable in two different always blocks. Just add rst to the sensitivity list. something like follows:

// sensitive to clock and reset both
always @ ( posedge clk, posedge rst )
        begin   
        if ( ~rst )   
            begin     
            count <= count << 1;    
            count[0] <= count[5];   
        end 
          else 
            count <= 8'b1;
    end

Using edge sensitive always blocks results in flip-flop creation. If this is done in two different blocks, then synthesis issues shall occur. This can be visualized by the logic you want in terms of gates and registers.

Also, during the clock generation, use of bitwise negation is recommended (~).

The ! symbol represents boolean or logical negation. While ~ symbol represents bitwise negation. 

// Replace this
always #1 clk = !clk;
// With this
always #1 clk = ~clk;

Applying rst after 20ns and terminating the simulation after 20ns shall not be what you want. You may want to use #200 $finish; instead.

These were some of the points I wanted to make clear. I simulated the code at EDAPlayground here, maybe you want to see the waveforms, which seems to be according to the one described in question.

More guidelines about synthesis can be obtained from this PDF.

Refer Always block hardware implementation and Difference in negation operators links for further information.

Upvotes: 1

droidmainiac
droidmainiac

Reputation: 328

https://gist.github.com/vividvilla/4605985

This should work, It contains both the test bench as well as the output for the program :)

Upvotes: 0

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