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Ratata Tata
Ratata Tata

Reputation: 2879

digital circuit scheme to vhdl ring counter multiplexer

I have this circuit that I want to implement in vhdl. There is a clock input and which clock event changes the 1 pin output sequentially. 0001 -> 0010 -> 0100 -> 1000 ...

clock multiplexer

I wondering what is the correct approach to do that. I could do that with multiple ifs and elsifs and an integer counter signal. Sorry for the noob question, is there a name for this kind of circuit?

Upvotes: 1

Views: 412

Answers (1)

user1155120
user1155120

Reputation:

It appears from your description this intended to be a ring counter. Your gates seem superfluous:

library ieee;
use ieee.std_logic_1164.all;

entity ring_counter is
    port (
        clk:    in  std_logic;
        q:      out std_logic_vector (0 to 3)
    );
end entity;

architecture your_representation of ring_counter is
    signal qint: std_logic_vector (0 to 3) := "0000";
    signal all_zero:        std_logic;
begin
YOURS:
    process(clk)
    begin
        if rising_edge(clk) then
            qint(0) <= qint(3);
            qint(1) <= all_zero or qint(0);
            qint (2 to 3) <= qint(1 to 2);
        end if;
    end process;

    all_zero <= '1' when qint = "0000" else
                '0';

    q <= (qint(0) or all_zero) & qint(1 to 3);
end architecture;

With a test bench:

library ieee;
use ieee.std_logic_1164.all;

entity ring_counter_tb is
end entity;

architecture foo of ring_counter_tb is
    signal clk:     std_logic := '0';
    signal q:       std_logic_vector(0 to 3);
begin
DUT:
    entity work.ring_counter(your_representation)
        port map (
            clk => clk,
            q => q
        );
CLOCK:
    process
    begin
        wait for 10 ns;
        clk <= not clk;
        if Now > 200 ns then
            wait;
        end if;
    end process;

end architecture;

Gives:

your representation in VHDL (clickable)

While a classic ring counter:

architecture classic of ring_counter is
    signal qint: std_logic_vector (0 to 3) := "1000";
begin
RING_CTR:
    process(clk)
    begin
        if rising_edge(clk) then
            qint <= qint(3) & qint(0 to 2);
        end if;
    end process;

    q <= qint;

end architecture;

(and modified test bench):

    entity work.ring_counter(classic)

gives:

ring counter classic (clickable)

And the starting phase is all in the initial condition.

Upvotes: 2

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