Getting U for signal value in VHDL simulation

Question

I'm trying to do xilinx provided student labs and I'm having trouble with writing this test bench. The actual source code works when I test it out on my Nexys 4. Writing a test bench for it is a later lab that I am working on now.

The source code is as follows

    entity ripple_carry_adder is
        Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
               b : in STD_LOGIC_VECTOR (3 downto 0);
               cin : in STD_LOGIC;
               s : out STD_LOGIC_VECTOR (3 downto 0);
               cout : out STD_LOGIC);
    end ripple_carry_adder;

    architecture Behavioral of ripple_carry_adder is
    component carry_look_ahead_4bit port (
        a : in STD_LOGIC_VECTOR;
        b : in STD_LOGIC_VECTOR;
        cin : in STD_LOGIC;
        cout : out STD_LOGIC;
        c : out STD_LOGIC_VECTOR);
    end component;

    component fulladder_dataflow port (
        a : in STD_LOGIC;
        b : in STD_LOGIC;
        cin : in STD_LOGIC;
        s : out STD_LOGIC;
        cout : out STD_LOGIC);
    end component;

    signal c : STD_LOGIC_VECTOR (2 downto 0);
    begin
    lookahead : carry_look_ahead_4bit port map (a, b, cin, cout, c);
    fa0 : fulladder_dataflow port map(a(0), b(0), cin, s(0), open);
    fa1 : fulladder_dataflow port map(a(1), b(1), c(0), s(1), open);
    fa2 : fulladder_dataflow port map(a(2), b(2), c(1), s(2), open);
    fa3 : fulladder_dataflow port map(a(3), b(3), c(2), s(3), open);

    end Behavioral;

My test bench is as follows

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.std_logic_textio.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_SIGNED.ALL;
    use STD.textio.ALL;

    entity ripple_carry_adder_tb is
    --  Port ( );
    end ripple_carry_adder_tb;

    architecture Behavioral of ripple_carry_adder_tb is
        component ripple_carry_adder port (
            a : in STD_LOGIC_VECTOR;
            b : in STD_LOGIC_VECTOR;
            cin : in STD_LOGIC;
            s : out STD_LOGIC_VECTOR;
            cout : out STD_LOGIC);
        end component;

        Signal ainput, binput : STD_LOGIC_VECTOR (3 downto 0) := "1111";
        Signal cinput : STD_LOGIC := '0';
        Signal sum_out : STD_LOGIC_VECTOR (4 downto 0) := "00000";

        procedure expected_output (
            ain, bin : in STD_LOGIC_VECTOR (3 downto 0 );
            cin : in STD_LOGIC;
            sum : out STD_LOGIC_VECTOR (4 downto 0)) is

        variable expected_s : STD_LOGIC_VECTOR (4 downto 0) := "00000";
        variable expected_cout : STD_LOGIC := '0';

        begin
        sum := ('0' & ain) + ('0' & bin) + ("0000" & cin);
        end expected_output;

    begin
        uut: ripple_carry_adder PORT MAP (
            a => ainput,
            b => binput,
            cin => cinput,
            s => sum_out(3 downto 0),
            cout => sum_out(4));

        process
            variable s : line;
            variable proc_out : STD_LOGIC_VECTOR (4 downto 0);

        begin
            expected_output(ainput, binput, cinput, proc_out);
            wait for 50 ns;
            if  (sum_out = proc_out) then
                write (s, string'("Test Passed")); write (s, string'("Expected: ")); write (s, proc_out); write (s, string'("Actual: "));         write (s, sum_out);
                writeline (output, s);
            else
                write (s, string'("Test Failed")); write (s, string'("Expected: ")); write (s, proc_out); write (s, string'("Actual: ")); write (s, sum_out);
                writeline (output, s);
            end if;

        end process;

    end Behavioral;

When I run the simulation, with a and b both set to 1111, I expect sum_out to become 11110. However, what I'm getting is 1UUU0. I think the problem is somewhere in the source code's signal 'c' not reaching fa1, fa2, and fa3 somehow but I don't know where to start in debugging this kind of problem. Your help is greatly appreciated!

EDIT:

Below is the carry_look_ahead

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity carry_look_ahead_4bit is
        Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
               b : in STD_LOGIC_VECTOR (3 downto 0);
               cin : in STD_LOGIC;
               cout : out STD_LOGIC;
               c : out STD_LOGIC_VECTOR (2 downto 0));
    end carry_look_ahead_4bit;

    architecture Behavioral of carry_look_ahead_4bit is
    signal p, g : STD_LOGIC_VECTOR (3 downto 0);
    signal cs : STD_LOGIC_VECTOR (2 downto 0);
    begin
    p <= a or b;
    g <= a and b;
    c(0) <= g(0) or (p(0) and cin);
    c <= cs;
    c(1) <= g(1) or (p(1) and cs(0));
    c <= cs;
    c(2) <= g(2) or (p(2) and cs(1));
    c <= cs;
    cout <= g(3) or (p(3) and cs(2));

    end Behavioral;

And Below is the fulladder code:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity fulladder_dataflow is
        Port ( a : in STD_LOGIC;
               b : in STD_LOGIC;
               cin : in STD_LOGIC;
               s : out STD_LOGIC;
               cout : out STD_LOGIC);
    end fulladder_dataflow;

    architecture Behavioral of fulladder_dataflow is

    begin
        s <= a xor (b xor cin);
        cout <= (a and cin) or (b and cin) or (a and b);

    end Behavioral;

Getting U for signal value in VHDL simulation

Answers (1)

Related Questions