CODEWITHSUNDEEP
stringmacrosverilogsystem-verilog
user5888527
user5888527

Reputation: 93

Systemverilog: Is there a way to make signal unique in macro instantiating a module?

I have a macro like this:

`define BOB_STAGE(_BUS_IN, _BUS_OUT) \
   bob_module auto_``_BUS_OUT``_bob_module ( .bus_in(_BUS_IN), .bus_out(_BUS_OUT) );

(Notice _BUS_OUT becomes part of the instance name to make unique instances.)

So these are used all over the place and take concatenated signals in to 1 signal out, but the out signal is indexed.

Example Use:

`BOB_STAGE( {A,B,C,D}, OUT[1] );

The problem is both the concat {} and index [] mess up the automatic assignment in the module instance name.

I want to solve this without adding another input for signal name and without temporary signals on the outside of the macro.

Is there some way to convert the output signal name with the index to a unique string... such as with $sformatf and then replace the index brackets with underscores?

Or is there some other way to uniqify the signal name but keep it legal? Something like atoi() to make it a unique number based off the signal name?

Upvotes: 0

Views: 1051

Answers (2)

dave_59
dave_59

Reputation: 42698

You can escape the name to allow symbols in an identifier

`define BOB_STAGE(_BUS_IN, _BUS_OUT) \
   bob_module \auto_``_BUS_OUT``_bob_module ( .bus_in(_BUS_IN), .bus_out(_BUS_OUT) );

`BOB_STAGE( {A,B,C,D}, OUT[1] );

will become

bob_module \auto_OUT[1]_bob_module ( .bus_in(_BUS_IN), .bus_out(_BUS_OUT) );

This is really the limit of what you can do for creating identifiers in SystemVerilog.

Upvotes: 1

Karan Shah
Karan Shah

Reputation: 1992

You can add one more argument to the macro to solve the issue.

Your macro may look like this: 

`define BOB_STAGE(_BUS_IN, _BUS_OUT, _NO) \
   bob_module auto_``_BUS_OUT``_``_NO``_bob_module ( .bus_in(_BUS_IN), .bus_out(_BUS_OUT[_NO]) );

Now your macro usage will look like this: 

`BOB_STAGE( {A,B,C,D}, OUT, 1 );

Upvotes: 0

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