CODEWITHSUNDEEP
macrosverilogsystem-verilog
rtmot
rtmot

Reputation: 11

Concatenate signal names in systemverilog using macro

I am trying to concatenate two strings in systemverilog/verilog to create a signal names. In my below code snippet, the lhs side seem to work fine, but the rhs side doesn't. The tool gives an error "bitemp has not been declared yet".

If i pass a hardcorded value say "0" to "clno" parameter, then it works for both lhs and rhs. 

enter code here
`define strcat_assign_macro(lhs_prestr,lhs_poststr,rhs_prestr,rhs_poststr,clno)  \
 assign lhs_prestr``clno``lhs_poststr = rhs_prestr``clno``rhs_poststr;

module tempmod;
  wire a0temp,b0temp;
  wire a1temp,b1temp;
  wire a2temp,b2temp;

  assign b0temp =1'b1;

  genvar i;
  generate
    for(i = 0; i < 3; i++)
    begin
      `strcat_assign_macro(a,temp,b,temp,i)
    end
  endgenerate


  initial begin
   $display (a0temp );
  end

endmodule

Upvotes: 1

Views: 2638

Answers (2)

Karan Shah
Karan Shah

Reputation: 1992

Since `defines are expanded before compilation, you are getting those errors.

One way to avoid that is to use a script to automate the define usage and use the same define in the Verilog file.

Here is a sample shell script, which I have made for this purpose. It is a basic script, but I think is sufficient to get you the idea.

#!/bin/csh

set b='`'
set a=`egrep -n "^ *${b}strcat_assign_macro" $2 | cut -d: -f1`
set line=`egrep -n "${b}strcat_assign_macro" $2 | cut -d: -f2`

foreach i (`seq $1`)
  set c=`expr $a + $i`
  sed -i "${c}i${line}" temp.ip
  sed -i "${c}s/^\(.*\), *[0-9]* *)/\1, ${i})/g" temp.ip
end

Here is the file before & after script.

// Before 
karan
shah
   `strcat_assign_macro(b, temp, a, temp, 0)
maheshbhai

// ./temp.sh <Extra Define Lines> <FileName>
./temp.sh 2 input.v

// After
karan
shah
   `strcat_assign_macro(b, temp, a, temp, 0)
`strcat_assign_macro(b, temp, a, temp, 1)
`strcat_assign_macro(b, temp, a, temp, 2)
maheshbhai

Upvotes: 0

dave_59
dave_59

Reputation: 42698

Macros get expanded before parsing any Verilog/SystemVerilog syntax. Use an array of wires.

Upvotes: 0

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