CODEWITHSUNDEEP
verilogfpgaxilinx
gambhirprateek
gambhirprateek

Reputation: 25

How do I correctly use `always` blocks?

The following is a snippet from a code I wrote in verilog for XST. The log is full of errors. How do I correct the code? How and where do I use always@() and @() blocks? Where do I use blocking and non blocking assignments?

input wire CLOCK;
input wire [31:0] OUT_SQRT;
output wire [31:0] IN_SQRT;
input wire [31:0] RANDP;

integer randp;
integer flagp;
integer sqrootp;
integer check_primep;

always @(posedge CLOCK and flagp != 0)
begin
    #10
    @(posedge and flagp != 0 )
    begin
        flagp = sqrootp%check_primep;

        if(flagp != 0 and check_primep < sqrootp)
        begin
            check_primep = check_primep + 1;
        end

        @(posedge and flagp == 0)
        begin
            flagp = 1;
            check_primep = 2;
            randp = RANDP;
            #5
            IN_SQRT = randp;
            #10
            sqrootp = OUT_SQRT;
        end
end

Upvotes: 0

Views: 318

Answers (1)

Morgan
Morgan

Reputation: 20514

A flip-flop is implied using:

always @(posedge clk) begin
  flip_flop_q <= flip_flop_d;
end

To make some thing synchronously (sampled on the clock) enabled:

always @(posedge clk) begin
  if (flagp != 0) begin
    flip_flop_q <= flip_flop_d;
  end
end

Combinatorial logic is implied using:

always @* begin
  comb_logic = a + b;
end

Things like the following (delays) are not synthesizable:

#10
@(posedge and flagp != 0 ) // no always just a delay waiting for criteria

Often used in test harnesses to wait for signals like resets etc being released.

initial begin
  @(posedge reset_n);
  @(posedge clk);
  @(posedge clk);
  //begin test procedure
end

If you need to wait for a signal in synthesisable verilog you need to build a FSM (Finite State Machine) to sequence your logic.

Upvotes: 1

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