CODEWITHSUNDEEP
arraysvhdlwrapper
defy313
defy313

Reputation: 11

Port mapping sub elements of array in specific order in VHDL?

So, I am writing a wrapper for a component. The component has some input in form of array like

-- Definition in the original component
array_1 : out std_logic_vector (1 downto 0);
array_2 : out std_logic_vector (1 downto 0);

I am trying to assign sub elements of array in port map as

-- All foo1, foo2, bar1, bar2 are defined as output std_logic in wrapper port list
array_1 (0) =>   foo1,
array_2 (0) =>   bar1,
array_1 (1) =>   foo2,
array_2 (1) =>   bar2,

The above produces an error like: formal association is made more than once

But weirdly, the following compiles fine.

array_1 (0) =>   foo1,
array_1 (1) =>   foo2,
array_2 (0) =>   bar1,
array_2 (1) =>   bar2,

Am I missing something, I can't find anywhere that the sub elements of an array have to be associated together but I can't find an example in which they are not. I know I could just do the latter but I am curious. Any help would be appreciated.

BTW, this is a short example I made up... the original code has over 50 elements but I have narrowed the problem to this. Thanks for any help or suggestions.

Upvotes: 1

Views: 1900

Answers (1)

user1155120
user1155120

Reputation:

A Minimal, Complete, and Verifiable example:

library ieee;
use ieee.std_logic_1164.all;

entity assoc_elements is
    port (
        array_1 : out std_logic_vector (1 downto 0);
        array_2 : out std_logic_vector (1 downto 0)  -- ;
    );
end entity;

architecture nothing of assoc_elements is
begin
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity element_assoc_test is
end entity;

architecture test of element_assoc_test is
    signal foo1, foo2, bar1, bar2: std_logic;
begin
ASSOC:
    entity work.assoc_elements
        port map (
            -- All foo1, foo2, bar1, bar2 are defined as output std_logic in wrapper port list
            array_1 (0) =>   foo1,
            array_2 (0) =>   bar1,
            array_1 (1) =>   foo2,
            array_2 (1) =>   bar2    -- ,
        );
end architecture;

Which gives us:

ghdl -a --std=08 assoc_elements.vhdl
assoc_elements.vhdl:30:30: non consecutive individual association for port "array_1"
ghdl: compilation error

Smugness aside on a tool giving a better error message, the LRM reference -

IEEE Std 1076-2008 6.5.7 Association lists, 6.5.7.1 General para 16:

A formal interface object shall be either an explicitly declared interface object or member (see 5.1) of such an interface object. In the former case, such a formal is said to be associated in whole. In the latter cases, named association shall be used to associate the formal and actual; the subelements of such a formal are said to be associated individually. Furthermore, every scalar subelement of the explicitly declared interface object shall be associated exactly once with an actual (or subelement thereof) in the same association list, and all such associations shall appear in a contiguous sequence within that association list. Each association element that associates a slice or subelement (or slice thereof) of an interface object shall identify the formal with a locally static name.

Which tells us element association must be contiguous which is the case in snippet you show that does analyze while the element association that fails is interleaved by element.

Upvotes: 3

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