CODEWITHSUNDEEP
verilogfpgaasic
Thang Nguyen Toan
Thang Nguyen Toan

Reputation: 39

Bit width different in verilog

What is different between {a + b} and (a + b) in verilog. I used the simulation to do:

reg [3:0] a = 4'b0001;
reg [3:0] b = 4'b1111;
reg [4:0] c = (a + b); give the result c = 5'b1_0000

but

reg [4:0] c = {a + b}; give c = 5'b0_0000;

It means the (a + b) can give the result 5 bits, but {a + b} give 4 bits. I don't know why. Please help me.

Thank you

Upvotes: 2

Views: 3060

Answers (1)

dave_59
dave_59

Reputation: 42623

Each expression in a concatenation is self-determined. {expr1,expr2, ...}. In your example, there is just one expression, and it happens to be a + b. According to Section 11.6 Expression bit lengths in the IEEE 1800-2012 LRM , L(a+b) in a self-determined context is Max(L(a),L(b)), which is 4 bits. Otherwise it is 5 bits in a context of an assignment.

Upvotes: 3

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