CODEWITHSUNDEEP
fifochisel
Dennis Skey
Dennis Skey

Reputation: 31

chisel asynch fifo / multiple clocks.

Does Chisel support multiple clocks in a design, yet? If I wanted to implement an asynchronous fifo how would one going about doing that in Chisel?

Upvotes: 3

Views: 875

Answers (1)

FabienM
FabienM

Reputation: 3741

Yes Chisel support multiple clocks in a design. If you want to use an asynchronous fifo you can import module ChiselUtil, it contain an asynchronous fifo : https://github.com/ucb-bar/chisel/blob/master/src/main/scala/ChiselUtil.scala#L599

To change clock domain for a register, use the argument clock of Reg() :

val s1 = Reg(init = UInt(0), clock = clockB)

See more information in tutorial chapter 16.

Upvotes: 2

Related Questions