CODEWITHSUNDEEP
veriloghdlsynthesis
vlsi_user
vlsi_user

Reputation: 73

Is event trigger synthesizable in verilog?

I am trying to use event triggering in my code (->). Will this get synthesized? 

always @(posedge clk) begin
count <= count + 1;
-> x;
end

always @(x) flag = 1;

This is just a sample code. What i want to do is when ever there is an event in the count I want to make the flag high, else it should remain low. In my case the count value increases after every 7 clock cycles. Can i use event triggering for this? If not what can I do to meet my requirement?

Upvotes: 0

Views: 1881

Answers (3)

dave_59
dave_59

Reputation: 42698

Anything you can execute in simulation could be synthesized if tools choose to support it. But most RTL synthesis tools do not support this.

In your simple case, you could replace your event trigger with a task call (or void function call in SystemVerilog).

 always @(posedge clk) begin
  count <= count + 1;
  x;
end
task x;
flag <= 1;
endtask

Upvotes: 0

noobuntu
noobuntu

Reputation: 913

You should not do this in synthesizable code. While some tools may be able to create equivalent logic, there is almost always an alternative that should be used instead. For example, your code can be rewritten as:

always @(posedge clk) begin
  count <= count + 1;
  -> x;
end

always @(count) flag = 1;

Upvotes: 0

FabienM
FabienM

Reputation: 3751

Some software can maybe synthesize it, but it's not a good code. If you do that, your code is not synchronous. To be synchronous, all «always» statement must toggle on the same edge of clk.

Upvotes: -1

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