CODEWITHSUNDEEP
verilogsystem-veriloghdl
Rudy Montoya
Rudy Montoya

Reputation: 85

Concatenating unbounded signals in Verilog, (Synthesizable)

I was wondering if you know other logic for the following operation:

Given 7 signals:

logic [7:0] in0, in1, in2;

logic [2:0] len0, len1, len2;

logic [31:0] out

Perform a concatenation of 3 in signals such that

out = {0...0, in2[len2:0], in1[len1:0], in0[len0:0]}

0...0 is zero padding. I can only think of out = 31'd0 | in2<<(len1+len0) | in1<<(len0) | in0 but I was wondering if there is another way to do this concatenation. I am okay with a multi-cycle approach. I just wanted to see if there is a faster/smaller area as an implementation for this operation.

Upvotes: 0

Views: 80

Answers (1)

dave_59
dave_59

Reputation: 42698

The only syntax currently synthesizable for doing this is mask/shift/or, or a set of for loops.

out = (in2 & (1<<len2)-1) << len0+len1 |
      (in1 & (1<<len1)-1) << len0 |
      (in0 & (1<<len0)-1);

Any way you do it results in a lot of multiplexers.

Upvotes: 2

Related Questions