CODEWITHSUNDEEP
verilogxilinxhdltest-bench
J. Doe
J. Doe

Reputation: 23

Verilog TestBench Error

Hello I am writing a Verilog Program in Xilinx and cannot get the testbench to produce work. 

    module Lab3(
    input  u,
    input clk,
    input clrn,

    output wire a,b,c,d,e,f,g

    );

    wire  dff3_combo;
    wire q_to_q;


    dff3 d0(
    .ns(dff3_combo),
    .clr(clrn),
    .clk(clk),
    .q(q_to_q)
        );


    combo_circuit combo(
    .q(q_to_q),
    .u(u),
    .ns(dff3_combo),
    .a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g)
    );
    endmodule

This was my attempt at a testbench. The simulation did not work, though u_tb, clock_tb and clr_tb kept their values.

    `timescale 1ns / 1ps

    module testbench ( );
reg u_tb,clr_tb, clock_tb;
wire a,b,c,d,e,f,g;


Lab3 L(
.u(u_tb),
.clk(clock_tb),
.clrn(clr_tb),
.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g)
);


always
begin
clock_tb = 1'b1;
#1;
clock_tb = 1'b0;
#1;
end

initial
begin
u_tb = 1;
clr_tb = 0;
#1 u_tb = 1;
#16 clr_tb = 0;
#20 $finish;
end
endmodule

My professor has not told us how to write this testbench, and I am very confused. Any help is appreciated.

Thanks

Upvotes: 0

Views: 739

Answers (1)

Rich Maes
Rich Maes

Reputation: 1222

Rewrite your clock like this

initial
   begin
     clk = 0;
     #5
     forever clk = #5  ~clk;
   end

Then instead of pausing (#1) between each of your input signal changes, try this instead

repeat (1) @ (posedge clk);

because you want to always setup right after a clock edge.

So your test proceedure initial statement will look more like

initial
begin
u_tb = 1;
clr_tb = 0;
repeat (1) @ (posedge clk);
u_tb = 1;
repeat (8) @ (posedge clk);
clr_tb = 0;
repeat (5) @ (posedge clk);
$finish;
end

See if that gets you going.

Upvotes: 0

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