CODEWITHSUNDEEP
system-veriloguvm
haykp
haykp

Reputation: 455

Nice way for accesing interface path

Please help to find a solution, for having nice looking code.

So in my code I have to do several forcing, as the same wire is being driven by tb and other part of design. As a result I have lots of force statements like this:

force TOP.u_proto_mc_top.gtx_rx_reset = TOP.u_proto_mc_top.u_GTX_RXB.gtxMaster_itf_inst.rstn;

force TOP.u_proto_mc_top.gtx_tx_reset = TOP.u_proto_mc_top.u_GTX_RXB.gtxMaster_itf_inst.txstn;

So I am just copy pasting the same interface path again and again, I mean this path: TOP.u_proto_mc_top.u_GTX_RXB.gtxMaster_itf_inst

Each time I need to force a interface signal, I have to copy and paste this path. This is ugly to me. Can someone please suggest another solution to this, for I don’t copy/paste the interface path again and again.

Thanks

Upvotes: 0

Views: 4537

Answers (2)

hevangel
hevangel

Reputation: 93

You can use uvm_hdl_read() and uvm_hdl_force() instead? Those UVM built-in function takes a string as input argument for the hdl path. 

string if_path = "TOP.u_proto_mc_top.u_GTX_RXB.gtxMaster_itf_inst";
string top_path = "TOP.u_proto_mc_top";
uvm_hdl_data_t val;

uvm_hdl_read({if_path,".rstn"}, val);
uvm_hdl_force({top_path, ".gtx_rx_reset", val);

uvm_hdl_read({path,".txstn"}, val);
uvm_hdl_force({top_path, ".gtx_tx_reset", val);

Upvotes: 1

dave_59
dave_59

Reputation: 42788

First I would try to find out why the structure of your testbench requires a force with an interface. Better planing could possibly avoid this.

A quick solutions use to use a text macro.

`define uTOP TOP.u_proto_mc_top 
`define GTXMaster `uTOP.u_GTX_RXB.gtxMaster_itf_inst
force `uTOP.gtx_tx_reset = `GTXMaster.txstn;

Upvotes: 2

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