CODEWITHSUNDEEP
system-veriloguvm
Somesh
Somesh

Reputation: 72

assign statement using virtual interface variable

I want to connect the module variable to the port in virtual interface using assign statement.

I created one interface and set it as virtual in config_db in my top module. I got the virtual interface via config_db in another module and trying to connect the port in another module to the port in the virtual interface

//Below is the sample code

  interface intf();   //Interface

       int values;

  endinterface

  module another_module();   //Another module

       virtual intf u_intf;

       int val;

       assign val = u_intf.values; //I am getting ERROR here

       initial begin
             uvm_config_db#(virtual intf)::get(null,"","assoc_array",u_intf);
       end

  endmodule

  module tb();           // Top TB

       intf u_intf();
       another_module u_another_module();

       initial begin
            uvm_config_db#(virtual intf)::set(uvm_root::get(),"","assoc_array",u_intf);
       end

  endmodule

Upvotes: 1

Views: 2168

Answers (1)

Serge
Serge

Reputation: 12344

Standard does not allow using virtual interfaces in assign statements. assign is used in verilog to connect different RTL blocks. virtual interface is a system verilog test bench concept. So, they cannot be mixed together.

You have to clarify, why you really need a virtual interface in this contents. They are not synthesizable. Are you writing a test bench module? In general case, you should use regular interfaces to connect modules.

However, in your example you can use always @* to do the assignment:

always @* val = u_intf.values;

Upvotes: 1

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