CODEWITHSUNDEEP
veriloghdlmodelsim
Rager925
Rager925

Reputation: 23

Error Loading Design when using module inside generate block

I have the following modules in separate files. When I try to run my RC_ADD_SUB_32 module, I get the error

Instantiation of 'inst' failed. Region: /RC_ADD_SUB_32_TB/obj/rc_gen_loop[0]/FULL_ADDER The design unit was not found. Error loading Design.

Instantiating the Full Adder does not work inside the generate block. I'm having trouble instantiating The Full Adder in the rc_add_sub_32.v file. Any ideas?

full_adder.v

module FULL_ADDER(S,CO,A,B, CI);
    output S,CO;
    input A,B, CI;

    wire HF_1_Y, HF_1_C, HF_2_C; //Half Adder 1 Y, Half Adder 1 C and Half Adder 2 C

    HALF_ADDER inst_01 (.A(A), .B(B), .Y(HF_1_Y), .C(HF_1_C));
    HALF_ADDER inst_02 (.A(HF_1_Y), .B(CI), .Y(S), .C(HF_2_C));
    or inst_03(CO, HF_2_C, HF_1_C);
endmodule;

rc_add_sub_32.v

module RC_ADD_SUB_32(Y, CO, A, B, SnA);
    // output list
    //output [63:0] Y;
    output [`DATA_INDEX_LIMIT:0] Y; //Our result
    output CO; 
    // input list
    //input [63:0] A;
    //input [63:0] B;
    input [`DATA_INDEX_LIMIT:0] A;
    input [`DATA_INDEX_LIMIT:0] B;

    input SnA;

    //full adder -> full adder connection
    wire [`DATA_INDEX_LIMIT:0] CO_TO_CI;
    wire [`DATA_INDEX_LIMIT:0] XOR_OUT;

    genvar i;
    generate
        for(i=0; i<32; i=i+1)
        begin: rc_gen_loop
        /*
            Cases:
            Index 0: CI is SnA  CO -> CI[1]
            Index 31: CI is CO from index 30, CO is output CO,
            Index 1-30: CI is from previous CO, CO points to next CI
        */ 
            xor xors(XOR_OUT[i], SnA, B[i]);
            if(i==0) 
            begin: 
                FULL_ADDER inst(.S(Y[i]), .CO(CO_TO_CI[i]), .A(A[i]), .B(XOR_OUT[i]), .CI(SnA));
            end
            else if(i==31) 
            begin:
                FULL_ADDER inst(.S(Y[i]), .CO(CO), .A(A[i]), .B(XOR_OUT[i]), .CI(CO_TO_CI[i-1]));
            end
            else if(i!=31 && i!=0) 
            begin:
                FULL_ADDER inst(.S(Y[i]), .CO(CO_TO_CI[i]), .A(A[i]), .B(XOR_OUT[i]), .CI(CO_TO_CI[i-1]));
            end
        end
    endgenerate
endmodule

The testbench file rc_add_sub_tb.v

module RC_ADD_SUB_32_TB;
    reg [`DATA_INDEX_LIMIT:0] A;
    reg [`DATA_INDEX_LIMIT:0] B;
    reg SnA;

    wire [`DATA_INDEX_LIMIT:0] Y;
    wire CO;

    RC_ADD_SUB_32 obj(Y, CO, A, B, SnA);

    initial
    begin
        #5 A = 0; B= 0; SnA = 0;
        #5 A = 0; B= 0; SnA = 1;
        #5 A = 0; B= 1; SnA = 0;
        #5 A = 0; B= 1; SnA = 1;
        #5 A = 1; B= 0; SnA = 0;
        #5 A = 1; B= 0; SnA = 1;
        #5 A = 1; B= 1; SnA = 0;
        #5 A = 1; B= 1; SnA = 1;
        #5;
    end
endmodule

Upvotes: 2

Views: 940

Answers (1)

Greg
Greg

Reputation: 19104

The condition statements have begin: without a label. As is, the simulator is either treating it as a blank label or line-wrapping and making FULL_ADDER as the label name. Both are are illegal. Either add a label (preferred) or get rid of the colon.

FYI, the if(i!=31 && i!=0) is unnecessary as the conditions were caught in the prior conditions.

Example with labels:

if(i==0) 
begin: gen_first
    FULL_ADDER inst(.S(Y[i]), .CO(CO_TO_CI[i]), .A(A[i]), .B(XOR_OUT[i]), .CI(SnA));
end
else if(i==31) 
begin: gen_last
    FULL_ADDER inst(.S(Y[i]), .CO(CO), .A(A[i]), .B(XOR_OUT[i]), .CI(CO_TO_CI[i-1]));
end
else 
begin: gen_middle
    FULL_ADDER inst(.S(Y[i]), .CO(CO_TO_CI[i]), .A(A[i]), .B(XOR_OUT[i]), .CI(CO_TO_CI[i-1]));
end

Or without labels:

if(i==0) 
begin
    FULL_ADDER inst(.S(Y[i]), .CO(CO_TO_CI[i]), .A(A[i]), .B(XOR_OUT[i]), .CI(SnA));
end
else if(i==31) 
begin
    FULL_ADDER inst(.S(Y[i]), .CO(CO), .A(A[i]), .B(XOR_OUT[i]), .CI(CO_TO_CI[i-1]));
end
else 
begin
    FULL_ADDER inst(.S(Y[i]), .CO(CO_TO_CI[i]), .A(A[i]), .B(XOR_OUT[i]), .CI(CO_TO_CI[i-1]));
end

Upvotes: 1

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