CODEWITHSUNDEEP
verilog
Vasanth
Vasanth

Reputation: 119

accessing elements of an multiply instantiated module

I am trying to write a behavioral code in verilog describing a RAM that has 256 locations, each of size 64-bits. so, I created a module RAM_cell that has output data_out and input data_in,both of width 64 bits. then, I created another module called RAM within which, I declared,

RAM_cell mem [255:0] (data_out,data_in,rd);

the RAM reads from 8-bit Maddr when rd=1 or writes to Maddrwhen rd=0.Now in the module RAM, which has Mdata_out as output, for read operation, I wrote,

always @(posedge clk)
initial
begin
if (rd == 1'b1)
Mdata_in = mem[Maddr].data_out;
end

that didn't work. the compiler threw error that the indexing variable is not a constant. Why didn't it work? what are the other ways (Other than using case statement using 256 control signals..!!).

Thank you. Any help will be highly appreciated.

PS: I can upload all necessary data (like exact code,compiler output,etc..) on demand.

Upvotes: 0

Views: 310

Answers (1)

Serge
Serge

Reputation: 12344

This is similar to the generate..endgenerate. the compiler allocates the number of instances you required. The array index will become a part of the name. So it will create 256 uniquely named instances like m[0], m[1], ... where '[]' will be just a part of the generated name. You cannot index into it. There is no such name as 'mem[Maddr]'

So, instead you should index your data_out.

I do not recommend using this construct at all due to confusing syntax around it. Instead use a generate block and a for loop to instantiate it. In this case you would have a complete control over what you pass to it:

generate
   for(geni = 0; geni < 256; geni++) begin: loop
        RAM_cell mem (data_out[geni],data_in[geni],rd);
   end


endgenerate

always @* begin
     ...
     Mdata_in = data_out[Maddr];
     ...
end

If you insist on XMR (non synthesizable) to access internal signals in the 'mem', you can put your always block inside the 'for' loop and use 'mem.sig'

Upvotes: 0

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