CODEWITHSUNDEEP
verilog
Oliver Perry
Oliver Perry

Reputation: 1

verilog : instantiation is not allowed in sequential area except checker instantiation

I'm trying to make a 4-bit input modulo 3 module. I keep getting the error "instantiation is not allowed in sequential area except checker instantiation". I'm not sure what I'm doing wrong.

module divisible_3(
   input [3:0] a,
   output div3);

wire xnor30;
wire xnor21;
wire and32;
wire xnor10;
wire xnor_and;
wire andxnor_and;

begin
always @ (*)

two_input_xnor xnor1 (a[3], a[0], xnor30);
two_input_xnor xnor2 (a[2], a[1], xnor21);

two_input_and and1 (a[3], a[2], and32);
two_input_xnor xnor3 (a[1], a[0], xnor10);

two_input_and and2 (xnor30, xnor21, xnor_and);
two_input_and and3 (and32, xnor10, andxnor_and);

two_input_or or1 (xnor_and, andxnor_and, div3);

end

endmodule

Upvotes: 0

Views: 4240

Answers (1)

spaceman
spaceman

Reputation: 88

I don't know what are you trying to do here, but you can not instantiate module inside an always block. It just doesn't make any sense. Also that begin statement has no functionality on the place where you've put it. It belongs inside the beginning of an always block. Whatever you are trying to do, just instantiate all of your modules outside the always block and it will be ok.

Upvotes: 2

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