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Marko Gulin
Marko Gulin

Reputation: 563

Declare a signal of the same type as another signal (VHDL)

Is it possible to declare a signal of the same type as another signal in VHDL?

For example, assume that we have the following signal declaration:

signal address_q : integer range 0 to 31;

I need to declare a variable address_d that will be of the same type as the address_q variable (integer range 0 to 31). Is it possible to do this by using built-in signal attributes, or in some other way?

Upvotes: 1

Views: 2031

Answers (2)

Renaud Pacalet
Renaud Pacalet

Reputation: 29230

The subtype attribute is probably what you are looking for:

entity foo is
end entity foo;

architecture bar of foo is
  signal address_q : integer range 0 to 31;
begin
  process
    variable v: address_q'subtype;
  begin
    report to_string(v'subtype'left);
    report to_string(v'subtype'right);
    wait;
  end process;
end architecture bar;

Simulation with GHDL:

foo.vhd:10:5:@0ms:(report note): 0
foo.vhd:11:5:@0ms:(report note): 31

Note: this attribute has been introduced in VHDL 2008. Do not try to use it with older versions of the VHDL standard.

Upvotes: 4

user3885596
user3885596

Reputation:

1st way:

You may declare more signals at once separating them by commas.

signal address_q, address_d : integer range 0 to 31;

2nd way:

You may declare your type first and then use it for all signal declarations.

type my_type is integer range 0 to 31;

signal address_q : my_type;
signal address_d : my_type;

Upvotes: 1

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