CODEWITHSUNDEEP
vhdl
DIWAKAR MISHRA
DIWAKAR MISHRA

Reputation: 65

How can we assign different signals to a single integer value?

I'm writing VHDL test bench for full adder

in Simulation i have tried this and getting the correct result

   begin        
            A <= '0';
            B <= '0';
            C <= '0';
            wait for 10 ns; 
            A <= '0';
            B <= '0';
            C <= '1';
            wait for 10 ns; 
            A <= '0';
            B <= '1';
            C <= '0';
            wait for 10 ns;
            A <= '0';
            B <= '1';
            C <= '1';
            wait for 10 ns;
            A <= '1';
            B <= '0';
            C <= '0';
            wait for 10 ns;
            A <= '1';
            B <= '0';
            C <= '1';
            wait for 10 ns;
            A <= '1';
            B <= '1';
            C <= '0';
            wait for 10 ns;
            A <= '1';
            B <= '1';
            C <= '1';
            wait for 10 ns;
      wait;
   end process;

but i don't want to write all this i just want to use for loop like in verilog

for i in 0 to 7 loop
    {A,B,C} <= i;  
    wait for 10 ns;
end loop;

I Know assigning A, B, C to i is not right in VHDL? how do we do that what are the correct syntax?

Upvotes: 3

Views: 187

Answers (3)

dalex78
dalex78

Reputation: 238

This work under VHDL93 with Vivado 2018.1:

loop1: for i in 0 to 7 loop
    (a,b,c) <= std_logic_vector(to_unsigned(i,3));
    wait for 10ns;
end loop;

You will not need the library use ieee.numeric_std_unsigned.all; (which I do not know) But you will need the standard ieee library:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

Here is the testbench:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; 
library work;

entity test_tb is

end entity;

architecture Behavioral of test_tb is

    signal clk : std_logic;
    signal a : std_logic;
    signal b : std_logic;
    signal c : std_logic;
begin

    clkpr : process
    begin
        clk <='1';
        wait for 10ns;
        clk <= '0';
        wait for 10ns;
    end process;

    test_pr : process
    begin

        loop: for i in 0 to 7 loop
            (a,b,c) <= std_logic_vector(to_unsigned(i,3));
            wait for 10ns;
        end loop;

        wait;
    end process;

end Behavioral;

Upvotes: 4

Tricky
Tricky

Reputation: 4471

Yes you can - VHDL 2008 allows aggregate assignments.

use ieee.numeric_std_unsigned.all;

for i in 0 to 7 loop
  (A,B,C) <= to_slv(i, 3);
  wait for 10 ns; 
end loop;

Upvotes: 4

Gautitho
Gautitho

Reputation: 623

You can try this :

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;    -- To use integer and unsigned

...

signal stimuli : std_logic_vector(2 downto 0); -- Equivalent of A, B, C

...

inst_full_adder : full_adder
port map
(
  i_a     => stimuli(0),
  i_b     => stimuli(1),
  i_carry => stimuli(2),
  ...
);

...

for i in 0 to 7 loop
  stimuli <= std_logic_vector(to_unsigned(i,3));  -- Conversion of your integer in std_logic_vector (3 is the size of your vector)
  wait for 10 ns;
end loop;

Upvotes: 2

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