Using Function for addition

Question

I am trying to use functions in Verilog to repeat a specific code logic which is Addition. I want to use a 4-bit binary adder in a function. I tried the following in Vivado, but it is strange that the output always has a one-bit value:

module my_divider(A,B,Sum); 

input [3:0] A;
input [3:0] B;
output [3:0] Sum;

function do_addition;
    input  [3:0] int_A,int_B; 
    reg   [3:0] v_Temp; // Local Variable
    begin    
       v_Temp = A + B;
       do_addition=v_Temp[3:0];
    end
  endfunction


assign Sum[3:0] = do_addition(A,B);
endmodule

Testbench is below:

module div_tb;

reg [3:0] A,B;
wire [3:0] Sum;
my_divider DUT(.A(A),.B(B),.Sum(Sum));

initial
begin
A=4'b0000;
B=4'b0000;
#50;
A=4'b0010;
B=4'b0001;
#50
A=4'b0001;
B=4'b1000;
end

initial
#150
$finish;

endmodule

output:

Is there something which I am missing?

The output is either 0 or 1. Is there some limitation of functions that I could pass only one bit?

Answer 1

You need to declare the function with a bit width:

function [3:0] do_addition;

Refer to IEEE Std 1800-2012, 13.4 Functions:

In particular, the implicit syntax can be empty, in which case the return type is a logic scalar.