CODEWITHSUNDEEP
intvhdlram
Sarvenaz
Sarvenaz

Reputation: 23

asking help for vhdl error

I am trying to write a code for RAM 16*4 on vhdl and the code is :

entity RAM_16_4 is
Port ( clk : in  STD_LOGIC;
       WR : in  STD_LOGIC;
       add : in  STD_LOGIC_VECTOR (3 downto 0);
       Di : in  STD_LOGIC_VECTOR (3 downto 0);
       Do : out  STD_LOGIC_VECTOR (3 downto 0));
end RAM_16_4;

architecture Behavioral of RAM_16_4 is

type RAM is array (15 downto 0) of std_logic_vector (3 downto 0);
 signal int : STD_LOGIC_VECTOR (3 downto 0);
 signal x : STD_LOGIC_VECTOR (3 downto 0);
begin

process (clk,WR)
begin

if ( clk'event and clk='1') then
if ( WR='1') then
int<= conv_integer (add);
int<= Di;
end if;
x<=add;
end if;
end process;

x<= conv_integer (add);
Do<= x;

end Behavioral;

This is the error which is coming: Type of int is incompatible with type of conv_integer.

how can I get rid of this error?

Upvotes: 2

Views: 262

Answers (1)

JHBonarius
JHBonarius

Reputation: 11271

conv_integer converts a std_logic_vector to an integer. You cannot assign that integer to a std_logic_vector. Why would you use conv_integer at all if you want to assign add to int or x? They are both the same type...

More important: please note that conv_integer is part of the non-standardized packages std_logic_arith or std_logic_unsigned, which you should not use. Instead you should use to_integer(unsigned(...)) from the standardized package numeric_std here.

When implementing a RAM for an FPGA, you should reference the FPGA manufacturers handbook. For instance from the Xilinx Synthesis User Guide

-- Single-Port RAM with Asynchronous Read (Distributed RAM)
-- File: rams_dist.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity rams_dist is
    port(
        clk : in std_logic;
        we : in std_logic;
        a : in std_logic_vector(5 downto 0);
        di : in std_logic_vector(15 downto 0);
        do : out std_logic_vector(15 downto 0)
    );
end rams_dist;

architecture syn of rams_dist is
    type ram_type is array (63 downto 0) of std_logic_vector(15 downto 0);
    signal RAM : ram_type;
begin
    process(clk)
    begin
        if (clk'event and clk = '1') then
            if (we = '1') then
                RAM(conv_integer(a)) <= di;
            end if;
        end if;
    end process;
    do <= RAM(conv_integer(a));
end syn;

...Well, crap.... Xilinx is also using the wrong conversion function. Let's rewrite that to standardized code:

-- Single-Port RAM with Asynchronous Read (Distributed RAM)
-- File: rams_dist.vhd
library ieee;
use ieee.std_logic_1164.all;

entity rams_dist is
    port(
        clk : in std_logic;
        we : in std_logic;
        a : in std_logic_vector(5 downto 0);
        di : in std_logic_vector(15 downto 0);
        do : out std_logic_vector(15 downto 0)
    );
end rams_dist;

architecture syn of rams_dist is
    use ieee.numeric_std.all;
    type ram_type is array (2**a'length-1 downto 0) of std_logic_vector(di'length-1 downto 0);
    signal RAM : ram_type := (others => (others => '0')); -- let's initialize it at zeros
begin
    ram_proc: process(clk)
    begin
        if rising_edge(clk) then
            if we = '1' then
                RAM(to_integer(unsigned(a))) <= di;
            end if;
        end if;
    end process;
    do <= RAM(to_integer(unsigned(a)));
end syn;

Upvotes: 2

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