CODEWITHSUNDEEP
verilogsynthesis
user3431800
user3431800

Reputation: 301

Is initial synthesizable in ASIC?

I haven't tried to synthesize myself but if someone could help to give a quick answer, that would be highly appreciated.

For a regular RAM, I see people do this in their Verilog, but I am told that initial is not synthesizable in Synopsys Design Compiler and I wonder if there is a difference among tools. Or this is doable just for memory initialization.

initial begin
    for (count=0;count<2048;count=count+1) RAM[count]=0;
end

This is specifically targeting ASIC instead of FPGA or Xilinx. Thanks in advance!

Upvotes: 0

Views: 1754

Answers (1)

user3885596
user3885596

Reputation:

No, it can be used for simulation purposes only. Synopsys Design Compiler does not synthesize initial blocks, it throws the following warning instead.

The statements in initial blocks are ignored.

Upvotes: 1

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