CODEWITHSUNDEEP
verilogsynthesize
Guanghua Shu
Guanghua Shu

Reputation: 95

Is Verilog code with disable named block operation synthesizable?

Is Verilog code with named block operation synthesizable? One such example is below:

 module named_block_disable();

 reg [31:0] bit_detect;
 reg [5:0]  bit_position;
 integer i;

 always @ (bit_detect)
   begin : BIT_DETECT
     for (i = 0; i < 32 ; i = i + 1) begin
       // If bit is set, latch the bit position
       // Disable the execution of the block
       if (bit_detect[i] == 1) begin
          bit_position = i;
          disable BIT_DETECT;
       end  else begin
          bit_position = 32;
       end
    end
  end

Upvotes: 1

Views: 1634

Answers (1)

dave_59
dave_59

Reputation: 42788

A named block is always synthesizable - it is the disable statement that may have issues with some tools. This usage to get out of a loop should be synthesizable. In SystemVerilog, you would use a break statement, which is definitely synthesizable. The for loop must be statically unrollable.

Upvotes: 1

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