CODEWITHSUNDEEP
verilogfsm
sandeep thagaram
sandeep thagaram

Reputation: 1

mixing of blocking and nonblocking issue and first bit of the 16-bit input is not being considered

This is my complete code. input 'h' is a 16 data bits and a sign bit.Some particular patterns are to be recognized in these databits. So each databit is taken into a FSM and checked for that particular pattern.

Now ,There are two issues here:

The first issue is that first data bit is never taken into consideration.

And the second issue is that variable 'i' is assigned with both blocking and non-blocking(without which code doesn't seem to work). Can someone please help with this.

 module formatting(x,h,sign,y0,y1,y2,y3,out1,out2,out3,out4,out5,
 ft1,ft2,ft3,ft4,ft5,bit1,bit2,bit3,bit4,bit5);

 input [16:0]x;
 input [0:16]h;
 output sign;
 output [15:0]y0,y1,y2,y3;
 output reg [1:0]out1,out2,out3,out4,out5;
 output reg [3:0]ft1,ft2,ft3,ft4,ft5;
 output reg  bit1,bit2,bit3,bit4,bit5;

 wire [15:0]x1;
 reg inp;
 integer i=0;
 reg [2:0]s=3'b0;
 reg [2:0]st=3'b0;
 reg [3:0]ft=4'b0;
 reg [2:0]cnt=3'b0;
 reg [1:0]out;

 assign  sign=(x[0]^h[16]);
 assign  x1=x[16:1];
 assign  y0=((x1>>3)+(x1>>1)+(x1>>2));
 assign  y1=(x1>>1);
 assign  y2=((x1>>1)+(x1>>3));
 assign  y3=((x1>>2)+(x1>>1));

 always@(i,h,inp) 
   begin
if(i<16) 
    begin
        inp<=h[i+1];
        i<=i+1;//non-blocking assignment of variable'i'
   case(s)
   3'b000:if(inp == 1'b1)
            begin
               if(i<=13)
                 begin
                   s=3'b001;
                   st=st+1'b1;
                   ft=i;

                 end        
               else if(i==14)
                 begin
                   s=3'b100;
                   st=st+1'b1;
                   ft=i;

                 end  
               else if(i==15)
                 begin
                   s=3'b000;
                   st=st+1'b1;
                   ft=i;
                   out=2'b01;
                   cnt=cnt+1'b1;

                 end  
             end    
          else 
                begin
                   s=3'b000;

                end    

   3'b001: if(inp == 1'b0)
            begin
               s=3'b010;

            end
          else
            begin
              s=3'b011;
            end                       

   3'b010:if(inp == 1'b1)
             begin
               s=3'b000;
               out=2'b10;
               cnt=cnt+1'b1;
             end
           else
             begin
             s=3'b000;
             out=2'b01;
             cnt=cnt+1'b1;
             end    

   3'b011:if(inp == 1'b1)
             begin
               s=3'b000;
               out=2'b00;
               cnt=cnt+1'b1;
             end 
           else  
             begin
              s=3'b000;
              out=2'b11;
              cnt=cnt+1'b1;
             end
   3'b100:if(inp == 1'b1)
              begin
               s=3'b000;
               out=2'b11;
               cnt=cnt+1'b1;
              end   
          else
              begin
               s=3'b000;
               out=2'b01;
               cnt=cnt+1'b1;
              end

    default:begin
                 s=3'b000;
                 out=2'bxx;
              end 
     endcase

     case(cnt)
             3'b001:begin
                      out1=out;
                      bit1=1'b1;
                    end 
             3'b010:begin
                     out2=out;
                     bit2=1'b1;
                    end 
             3'b011:begin
                      out3=out;
                      bit3=1'b1;
                    end
             3'b100:begin
                      out4=out;
                      bit4=1'b1;
                    end
             3'b101:begin
                      out5=out;
                      bit5=1'b1;
                    end 
             default:begin
                       out1=2'b00;bit1=1'b0;
                       out2=2'b00;bit2=1'b0;
                       out3=2'b00;bit3=1'b0;
                       out4=2'b00;bit4=1'b0;
                       out5=2'b00;bit5=1'b0;
                     end                                                                              
           endcase

            case(st)
             3'b001:begin 
                      ft1=ft;
                    end  
             3'b010:begin 
                      ft2=ft;
                    end  
             3'b011:begin 
                      ft3=ft;
                    end  
             3'b100:begin
                      ft4=ft;
                    end  
             3'b101:begin
                      ft5=ft;
                    end     
             default:begin
                       ft1=4'b0000;
                       ft2=4'b0000;
                       ft3=4'b0000;
                       ft4=4'b0000;
                       ft5=4'b0000;
                     end
           endcase
   end 
    else
     begin
       i=0;//blocking assignment of variable'i'
       st=3'b000;
       cnt=3'b000;
       ft=4'b0000;
       s=3'b000;
     end        
  end    
  endmodule

Upvotes: 0

Views: 145

Answers (1)

Oldfart
Oldfart

Reputation: 6259

You are taking about an FSM. In HDL an FSM is a piece of code/hardware which trundles though a number of states using a clock. Your code does not have a clock and as such is not a FSM.

That also causes the confusion in your blocking and non-blocking assignments. In a clocked section you use only non-blocking assignments. In a combinatorial section you use only blocking assignments.

I am afraid you have to seriously re-write the code thinking of what needs to be done in each step (clock). Also add a reset signal. That will set an initial state from which everything starts.

Also nowadays the use of always (*) or always_comb is preferred. The danger is that you forget a variable in your sensitivity list and then your simulation will not match with the hardware.

Without clock you have to write the whole section using a single for loop:

for (i=0; i<16; i=i+1)
begin
   // All logic expressed as a function of i
end

I foresee problems as you also have a case in there. HDL is as it says a Hardware Description Language. In the end you have a single piece of hardware which must do all the processing. Thus the synthesis tool must know all the hardware it must generate using compile time known values.

Upvotes: 1

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