CODEWITHSUNDEEP
verilogtest-bench
SWETHA CHILVERI
SWETHA CHILVERI

Reputation: 53

FSM not working as expected (sequence detector 0110)

I don't know what is wrong in the below code. It gives me output 1 only after adjusting my simulation delays properly. It gives me one after some different sequence. I cross-checked my logic several times. Please help me find my bugs.

output

code

module seq_0110(sequence_in,clock,reset,detector_out
    );
input clock; 
input reset; 
input sequence_in; 
output reg detector_out; 
reg [1:0] current_state, next_state; // current state and next state


always @(posedge clock, posedge reset)
begin
 if(reset==1) 
 current_state <=2'b00;// when reset=1, reset the state of the FSM to "Zero" State
 else
 current_state <= next_state; // otherwise, next state
end 

always @(current_state,sequence_in)
begin
 case(current_state) 
 2'b00:begin
  if(sequence_in==1)
   next_state <= 2'b00;
  else
   next_state <= 2'b01;
 end
 2'b01:begin
  if(sequence_in==1)
   next_state <= 2'b10;
  else
   next_state <= 2'b01;
 end
 2'b10:begin
  if(sequence_in==1)
   next_state <= 2'b11;
  else
   next_state <= 2'b01;
 end 
 2'b11:begin
  if(sequence_in==1)
   next_state <= 2'b00;
  else
   next_state <= 2'b01;
 end
 
 default:next_state <= 2'b00;
 endcase
end
// combinational logic to determine the output
// of the Moore FSM, output only depends on current state
always @(current_state)
begin 
 case(current_state) 
 2'b00:   detector_out <= 1'b0;
 2'b01:   detector_out <=1'b0;
 2'b10:  detector_out <= 1'b0;
 2'b11:  detector_out <=(sequence_in==1)?1'b0:1'b1;
 
 default:  detector_out <= 1'b0;
 endcase
end 
endmodule

Upvotes: 0

Views: 775

Answers (1)

toolic
toolic

Reputation: 61987

The problem is in your testbench and how you are displaying the signals in your log file.

In the testbench code you posted in your other Question earlier today, you used $monitor to print the input and output signal. The problem with that is $monitor only shows these signals if there is a change in either signal. In your case, it would be much more meaningful to show these signals once per clock cycle. This can be done using an always block and a $display, as follows:

always @(negedge clock) $display($time, " in=%b out=%b", sequence_in, detector_out);

initial begin
  $dumpfile("seq_0110.vcd");
  $dumpvars(0,seq_0110_t);
  sequence_in = 0;
  reset = 1;
  #30;
  reset = 0;

  repeat (5) @(posedge clock); sequence_in = 0;
             @(posedge clock); sequence_in = 1;
             @(posedge clock); sequence_in = 1;
             @(posedge clock); sequence_in = 0;

  repeat (5) @(posedge clock); sequence_in = 0;
             @(posedge clock); sequence_in = 1;
             @(posedge clock); sequence_in = 1;
             @(posedge clock); sequence_in = 0;

  repeat (5) @(posedge clock); sequence_in = 0;

  #10 $finish;
end

Now, the output clearly shows that your FSM detects the 0110 bit pattern on your input:

          10 in=0 out=0
          20 in=0 out=0
          30 in=0 out=0
          40 in=0 out=0
          50 in=0 out=0
          60 in=0 out=0
          70 in=0 out=0
          80 in=0 out=0
          90 in=1 out=0
         100 in=1 out=0
         110 in=0 out=1
         120 in=0 out=0
         130 in=0 out=0
         140 in=0 out=0
         150 in=0 out=0
         160 in=0 out=0
         170 in=1 out=0
         180 in=1 out=0
         190 in=0 out=1
         200 in=0 out=0
         210 in=0 out=0
         220 in=0 out=0
         230 in=0 out=0
         240 in=0 out=0

Upvotes: 1

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