CODEWITHSUNDEEP
verilogfpgastate-machinexilinx
narutouzumaki 99
narutouzumaki 99

Reputation: 107

Problems with sequence detector in verilog (finite state machine)

I wanted to make sequence detector that will detect three consecutive ones. When the sequence is detected, digital circuit stops and waits for a reset signal to be active, so it would detect sequence again. I wrote the code but it has some problems. In xvlog file, I have following errors:

"syntax error near ;" (for lines 23,25,27,29,35,47,48)

and

"default case should appear only once" (for lines 23,25,27,29,35,48,49).

Here is the code:

`timescale 1ns / 1ps

`define S0 3'd0;
`define S1 3'd1;
`define S2 3'd2;
`define S3 3'd3;
`define S4 3'd4;

module kolo1(out,in,r,clk);
output out;
reg out;
input in,r,clk;
reg [2:0] stanje,sledece_stanje;
initial
begin
stanje=`S0;
sledece_stanje=`S0;
out=0;
end
always @(stanje or r or in)
begin
case(stanje)
`S0: if(r) sledece_stanje=`S1;
     else sledece_stanje=`S0;
`S1: if(in) sledece_stanje=`S2;
     else sledece_stanje=`S0;
`S2: if(in) sledece_stanje=`S3;
     else sledece_stanje=`S0;
`S3: if(in) sledece_stanje=`S4;
     else sledece_stanje=`S0;
`S4: begin 
repeat(1) @(posedge clk);
sledece_stanje=`S0;
end
default: sledece_stanje=`S0;
endcase 
end

always @(posedge clk)
begin
stanje=sledece_stanje;
end

always @(stanje)
begin
case(stanje)
`S0,`S1,`S2,`S3: out=0;
`S4:out=1;
default: out=0;
endcase
end
endmodule

module stimulus;
reg clk,in,res;
wire out;

kolo1 k1(out,in,res,clk);

initial
clk=1'b0;

always 
#2 clk=~clk;

initial 
begin
$monitor($time,"out=%b in=%b res=%b clk=%b",out,in,res,clk);
in=0;res=0;
#2 res=1;
#20 res=0;
#5 res=1;
#30 $finish;
end

endmodule

Upvotes: 1

Views: 264

Answers (1)

toolic
toolic

Reputation: 62037

You should remove the semicolons from your define macros:

`define S0 3'd0
`define S1 3'd1
`define S2 3'd2
`define S3 3'd3
`define S4 3'd4

The complier does a simple text substitution. For example, whenever it sees `S0, it is replaced with 3'd0;. Thus,

`S0: if(r) sledece_stanje=`S1;

becomes:

3'd0;: if(r) sledece_stanje=`S1;

The ;: is a syntax error.

Upvotes: 1

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