CODEWITHSUNDEEP
verilog
David
David

Reputation: 27

Instantiating modules in a sub-directory

In Verilog, I understand that I can instantiate modules that are defined in other Verilog files that are in the same directory.

Let's say I have a 'top' module, and in the same directory as the module, I have a sub-directory with many more Verilog files. How can I instantiate modules from a file in the sub directory in the top module?

Upvotes: 1

Views: 1037

Answers (1)

kevin1494
kevin1494

Reputation: 158

Your top module can instantiate other modules that are present anywhere.

The only thing to take care of is: your verilog simulator should know where to pick up the required module definitions from. Otherwise it will likely fail in the compile stage and complain about the same.

Based on which simulator you are using, make sure you provide the appropriate paths where all your verilog modules are defined

Upvotes: 1

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